Using machine trained network during routing to modify locations of vias in an ic design

ABSTRACT

Some embodiments use a machine-trained network during routing to provide the router with sufficient information to improve the quality of routes generated by a router. This machine-trained network in some embodiments is referred to as the “digital twin” of a lengthy design and/or manufacturing process that produces the design of an IC layout and/or manufactures an IC based on a designed IC layout. The digital twin in some embodiments provides information regarding parasitics, regarding redundant vias for insertion or regarding complexity of subsequent manufacturing processes used to manufacture an IC based on the IC design layout.

BACKGROUND

An integrated circuit (“IC”) is a device that includes many electroniccomponents, such as transistors, resistors, diodes, etc. Thesecomponents are often defined on a semiconductor substrate andinterconnected with metal wiring and vias to form multiple circuitcomponents, such as gates, cells, memory units, arithmetic units,controllers, decoders, etc. An IC typically includes multiple layers ofwiring and vias that interconnect its electronic and circuit components.

Design engineers design ICs by transforming logical or circuitdescriptions of the IC components into geometric descriptions, calledlayouts. IC layouts typically include (1) geometric representations ofelectronic or circuit IC components (called circuit modules) with pins,and (2) geometric representations of wiring (called interconnect linesbelow) that connect the pins of the circuit modules. A net is typicallydefined as a collection of pins that need to be connected. To createlayouts, design engineers typically use electronic design automation(“EDA”) applications. These applications provide sets of computer-basedtools for creating, editing, and analyzing IC design layouts.

Fabrication foundries manufacture ICs based on these IC design layouts.To fabricate an IC after designing of the IC layout is completed,lithographic masks are created based on the IC layout so that the maskscontain various geometries that when used in lithographic processesproduce the various geometries of the IC layout on a semiconductorwafer. The produced geometries represent the elements (such as ICcomponents, interconnect lines, via pads, etc.) of the IC.

Even when the IC design layouts are otherwise valid, fabs cannot alwaysreliably manufacture ICs unless the IC design layouts effectivelyaccount for capabilities, settings and variances of the manufacturingprocesses employed by the fabs. When IC design layouts are completedwithout taking into account these manufacturing constraints, the ICdesign layouts at times need to be modified after they are completed andsent over to the fabs.

Wire routing, commonly called simply routing, is a critical step in thedesign of printed circuit boards (PCBs) and integrated circuits (ICs).It builds on a preceding step, called placement, which determines thelocation of each active element of an IC or component on a PCB. Afterplacement, the routing step adds interconnects in the design layout thatare needed to properly connect the placed components while obeying alldesign rules for the IC. Together, the placement and routing steps of ICdesign are known as place and route.

Routers are typically given some pre-existing polygons comprising pins(also called terminals) on cells, and optionally some pre-existingwiring called pre-routes. Each such polygons is typically associatedwith a net, usually by name or number. The router has to creategeometries such that all terminals assigned to the same net areconnected, no terminals assigned to different nets are connected, andall design rules are obeyed. A router can fail by not connectingterminals that should be connected (an open), by mistakenly connectingtwo terminals that should not be connected (a short), or by creating adesign rule violation.

In addition, to correctly connect the nets, routers are expected to makesure the design meets timing. Some of the biggest challenges in chipscaling involve contacts and interconnects. Since interconnects becomemore compact at each process node, this has an adverse effect on RCdelay (and hence timing, max operating frequency, etc.) in IC designs.Transistor devices have traditionally scaled well, e.g., with thetranslation from planar to FinFET devices. However, the contacts andinterconnects have shrunk as the devices have shrunk, which leads tosignificant increase in both resistance and capacitance. Foundries havebeen able to reduce the contribution to RC delay from resistancesomewhat by increasing the aspect ratio (effectively, the height) of theinterconnect - with a resulting increase in coupling capacitance - butresistance has become an increasingly difficult problem to solve. Theresistance problem is further confounded by misalignment issues whenmanufacturing multiple-layer designs. Both resistance and capacitancecombine to impact circuit timing and signal integrity, which negativelyimpacts a router’s ability to deliver a good solution.

As process geometries have shrunk, routers have faced additionalchallenges in the areas of signal integrity, manufacturability, andreliability. In particular, crosstalk issues are a primary concern inthe area of signal integrity, and these have arisen primarily due toincreases in coupling capacitances, which in turn have been driven byincreases in the aspect ratios of wires, combined with decreases in thelateral distances between them.

In terms of manufacturability, Optical Proximity Correction (OPC) hasbecome a primary concern, with routers needing to become OPC aware inorder to avoid creating problems for downstream OPC tools. OPC adds orsubtracts patterns to a mask to enhance the layout resolution andimprove the printability or transfer of the mask patterns to wafer.Chemical Metal Polishing (CMP) has also become a large manufacturabilityissue to which routers need to be aware. CMP strives to achieve layoutuniformity and chip planarization to achieve a good manufacturing yield.

Variability in manufacturing, which also increases as process nodes getsmaller, further negatively impacts a router’s ability to deliver a goodsolution that is robust in the face of manufacturing variations.Reliability issues face circuits during manufacture, or after they havebeen manufactured, and also need to be accounted for during routing.Routers need to minimize or eliminate antenna effects in order toprotect against dielectric breakdown, and redundant-via insertion hasalso become commonplace as one way to mitigate against via failures thatoccur due to a variety of reasons, including random defects, cutmisalignments during manufacturing, and thermal-stress orelectromigration issues afterwards.

All of these issues combine to make the task of routing ever moredifficult. There is clearly a need to have routers be aware of more andmore of these kinds of details, and to have better models/awareness ofthe issues, in order to allow the routers to achieve the best solutions.

BRIEF DESCRIPTION OF FIGURES

The novel features of the invention are set forth in the appendedclaims. However, for purposes of explanation, several embodiments of theinvention are set forth in the following figures.

FIG. 1 illustrates an example of a router in some embodiments that usesone or more digital twin machine-trained networks to generate routesand/or to evaluate the generated routes.

FIG. 2 illustrates an example of a curvilinearization of Manhattanshapes by manufacturing process.

FIG. 3 illustrates multiple trained neural networks that producemultiple predicted contours for the design layout shaped over multipleprocess variations.

FIG. 4 illustrates a process for obtaining the ground truth data fortraining the digital twin in some embodiments.

FIG. 5 illustrates examples of edge/corner-based OPC patterns in whichserifs, hammerheads and line biasing are inserted.

FIG. 6 illustrates an example of a global and (grid-based) detailedrouting that routes a path between the two circular pins in someembodiments.

FIG. 7 illustrates examples of detailed routing that are grid-based orgridless in some embodiments.

FIG. 8 illustrates examples of three design rules that are often checkedare component width, component spacing and enclosure spacing.

FIG. 9 illustrates an example of a top-down manner, a level by levelapproach for routing a 3-pin net.

FIG. 10 illustrates an example of a hybrid hierarchical approach torouting.

FIG. 11 illustrates an example of another common multi-level approachknown as A-shaped (Gamma) multi-level routing.

FIG. 12 illustrates an example of a contribution of a RC segment toElmore delay at a sink.

FIG. 13 illustrates an example of a crosstalk effect, a main source ofnoise.

FIG. 14 illustrates an example of an intermediate stage in A-shaped(Gamma) multi-level routing to minimize crosstalk.

FIG. 15 illustrates an example of a track assignment problem forcrosstalk minimization.

FIG. 16 illustrates an example of a potential solution to acrosstalk-aware track assignment problem.

FIG. 17 illustrates an example of a capacitance matrix between a shapeand other shapes, in which three semiconductor layers are represented.

FIG. 18 illustrates a neural network trained and used to infercapacitance values in some embodiments.

FIG. 19 illustrates an example of a 6-channel image that is input to thenetwork.

FIG. 20 illustrates a process that uses a digital twin MTN duringrouting to identify routes with acceptable parasitics.

FIG. 21 illustrates an example of a double-pair redundant via insertion.

FIG. 22 illustrates examples of ‘dead’ vias, ‘critical’ vias, and‘alive’ vias.

FIG. 23 illustrates an example of a process for redundant-via-awaredetailed routing.

FIG. 24 illustrates a process that some embodiments use to identifycandidate redundant via insertion locations.

FIG. 25 illustrates an example of an MTN processing the rasterizeddesign layout portion to identify locations for inserting vias in thedesign layout.

FIG. 26 illustrates an example of an MTN processing a rasterized imageof a rectilinear design layout to produce another rasterized image of acurvilinear design layout that represents the predicted manufactured ICassociated with the input design layout.

FIG. 27 illustrates a process of some embodiments that uses a digitaltwin MTN to just identify via hotspots, and then uses another process toanalyze the identified hotspots in order to add redundant vias, movevias or remove vias.

FIG. 28 illustrates a process for training a neural network to performthe operations of the via modification MTN of some embodiments.

FIG. 29 illustrates a process of some embodiments that uses a digitaltwin MTN to generate the predicted manufactured shapes of vias, and thenanalyzes these shapes to determine whether it needs to insert additionalredundant vias and/or to move any vias.

FIG. 30 illustrates examples of mask patterns without OPC and with(edge-based) OPC.

FIG. 31 illustrates an example of an optical proximity correction.

FIG. 32 illustrates an example of an ILT-based OPC output that shows amask before and after ILT.

FIG. 33 illustrates examples of images produced by an ILT-based digitaltwin that shows curvilinear ILT digital twin and the real curvilinearmask pattern generated from an industry leading ILT tool.

FIG. 34 illustrates a process for training a neural network to performan OPC operation to produce OPC-adjusted images for a routing solutionin some embodiments.

FIG. 35 illustrates a process for training an MTN to directly output anOPC cost for a routing solution.

FIG. 36 illustrates a process that a router uses during routing in someembodiments to account for OPC costs in its route selection operation.

FIG. 37 illustrates a process that a router of some embodiments uses toemploy such an MTN during routing.

FIG. 38 illustrates examples of a front-side power delivery, afront-side power delivery with buried power rails, and a back-side powerdelivery.

FIG. 39 illustrates an example of a maze-routing process that adopts atwo-phase approach to a routing problem.

FIG. 40 conceptually illustrates an electronic system with which someembodiments of the invention are implemented.

DETAILED DESCRIPTION

In the following detailed description of the invention, numerousdetails, examples, and embodiments of the invention are set forth anddescribed. However, it will be clear and apparent to one skilled in theart that the invention is not limited to the embodiments set forth andthat the invention may be practiced without some of the specific detailsand examples discussed.

Some embodiments use a machine-trained network (e.g., a neural networkor other machine-trained network) during routing to provide the routerwith sufficient information to improve the quality of routes generatedby a router. This machine-trained network in some embodiments isreferred to as the “digital twin” of a lengthy design and/ormanufacturing process that produces the design of an IC layout and/ormanufactures an IC based on a designed IC layout. The term “digitaltwin” connotes that the machine-trained network (MTN) is a digitalapproximation of this lengthy design and/or manufacturing process, andproduces approximations of the results that would be obtained had thedesign and/or manufacturing process been performed on the current IClayout to finish the IC design and/or manufacture the IC.

When predicting the manufactured shape of the IC layout, the digitaltwin in some embodiments predicts the shape of the components producedon the IC at a subsequent stage in the manufacturing process. Thissubsequent stage can be different in different embodiments. Forinstance, in some embodiments, this subsequent stage is a wafersimulation stage that produces the component shapes on a simulatedmanufactured wafer, while in other embodiments it is the actual ICmanufacturing stage that produces the actual components on amanufactured IC. The term digital twin can also be used to reflect thepredicted manufactured shapes. Whether the term refers to the overalldesign and/or manufacturing process, or the manufactured object/shape,will be clear from the context.

FIG. 1 illustrates that a router 100 in some embodiments uses one ormore digital twin machine-trained networks to generate routes and/or toevaluate the generated routes. Specifically, the router 100 is shown toinclude one or more route generation processes 105, one or more routeevaluation processes 110 and one or more machine-trained networks 115that are digital twins of one or more design and/or manufacturingprocesses.

Each route generation process 105 generates one or more routes in an ICdesign layout, while each route evaluation process 110 evaluates one ormore routes generated by one or more route generation processes toensure that the generated routes satisfy a set of design constraintswhile optimizing (e.g., maximizing or minimizing) an objective function.The design constraints in some embodiments place bounds on the solutionsthat are explored for optimizing objective functions. IC design layoutstypically include (1) geometric representations of electronic or circuitIC components (called circuit modules) with pins, and (2) geometricrepresentations of wiring (called interconnect lines below) that connectthe pins of the circuit modules. A net is typically defined as acollection of pins that need to be connected. Several examples of routegeneration processes and route evaluation processes that use digitaltwins are described below.

Routing solutions are analyzed to predict how resistance and capacitanceimpact timing, signal integrity, and other effects impact theperformance of the routes that are specified by the routing solutions.The route evaluation processes of some embodiments use digital twin MTNsto provide fast and reliable computation of the parasitic resistancesand capacitances, and/or prediction of how these parasitics impacttiming, signal integrity, and other effects. These route evaluationprocesses lead to improved routing solutions, improvements inroutability, reduction in routing time, etc.

Some embodiments perform such evaluations while routing individualroutes for individual nets. Other embodiments perform such evaluationsafter several routes have been defined for several nets. For instance,some embodiments perform such evaluations during rip-up and rerouteoperations that analyzes a design layout or a portion of the designlayout to identify any structures (e.g., routes, vias, etc.) that do notmeet certain criteria (e.g., parasitic criteria, via placement or sizecriteria, route cost criteria, etc.). For instance, during a rip-up andreroute operation, a router can analyze a group of routes to identifyproblematic routes, remove them from the design (i.e., “rip” theseroutes out of the design), and to identify new routes (i.e., tore-route) for the nets that had their routes removed. Rip-up and rerouteis often an iterative process, running until all nets are successfullyre-routed or a time limit/iteration count is exceeded, and often leadsto improved routing solutions.

The route generation processes 105 and/or route evaluation processes 110of some embodiments also use digital twin MTNs to generate predictedmanufactured shapes of IC design components, and then use these shapesto inform their route generation and/or route evaluation operations.Many of the IC designs today are created with rectilinear shapes, usingManhattan routing, or occasionally 45 degree routing. When these designsare manufactured, the shapes deposited on the substrate are no longerManhattan. In fact, the actual deposited shapes become highlycurvilinear, due to the realities of manufacturing, particularly atmodern process geometries.

FIG. 2 illustrates an example of a curvilinearization of Manhattanshapes by manufacturing process. This figure shows a user interface ofan EDA tool displaying rectilinear/Manhattan shapes withcross-hatchings, which in some embodiments are displayed in first andsecond colors, e.g., light blue and red. Superimposed on these Manhattanshapes are the actual or predicted manufactured shapes, which as shownare in the curvilinear forms illustrated by the contours that in someembodiments are displayed in other colors (e.g., lighter gray, gray anddarker gray).

In this example, the different-colored cross-hatched rectilinear shapesrepresent different color masks for a metal layer, while the three setsof curvilinear manufactured contours shown correspond to onemanufacturing process extreme (e.g., inner contour shown in darkergray), the nominal process conditions (e.g., the middle contour shown ingray) and the other manufacturing process extreme (e.g., the outercontour shown in lighter gray). Some embodiments use the curvilinearshapes to perform design rule checks during route generation and/orroute evaluation operations. U.S. Pat. Publication 20220128899, U.S.Pat. Application 17/992,870, U.S. Pat. Application 18/097,272, and U.S.Pat. Application 17/992,897 describe processes for generating predictedcurvilinear manufactured shapes for IC designs. U.S. Pat. Publication20220128899, U.S. Pat. Application 17/992,870, U.S. Pat. Application18/097,272, and U.S. Pat. Application 17/992,897 are all incorporatedherein by reference.

In some cases, the manufacturing processes variations that result inmultiple contours (inner, nominal, outer) combine with the process layermisalignment problem to result in poor via/contact overlaps. Whileinterconnect wiring traverses one metal layer that is commonly definedin terms of two axes (e.g., x- and y-axis), vias are conductivestructures that traverse in a third axis (z-axis) to connectinterconnect wirings that traverse along different layers and/orinterconnect wiring and pins on different layers. Some embodiments usedigital twin MTNs to produce the predicted via/contact overlaps in viewof the manufacturing processes variations and misalignment problems, asfurther described in U.S. Pat. Application 17/992,897, which isincorporated herein by reference.

The various degrees of curvature and proximity variation in themanufactured shapes become worse at smaller process nodes. Thisworsening makes it difficult to accurately predict the actualcapacitance values, and perhaps more importantly, the spread orvariation in capacitance values. This tends to result in added pessimismin resistance and capacitance models, which in turn adds pessimism totiming calculations, and so negatively impacts a router’s chances tofind a good enough solution in a reasonable timeframe.

As further described below, some embodiments use digital twin MTNs(e.g., neural networks) during routing to provide the router withsufficient information to improve the routability of designs, to improvethe routing quality of results, to reduce or eliminate timingviolations, to reduce or eliminate signal integrity (SI)-relatedviolations, and/or to reduce or eliminate manufacturing hot spots.

FIG. 3 illustrates that some embodiments use three different digitaltwin MTNs 305, 310 and 315 to produce for an input portion 300 of adesign layout, three different predicted contours 320, 325 and 330 thatare defined for three different process variations, as described aboveby reference to FIG. 2 . These three different MTNs generate thesecontours very quickly and accurately. The training and use of theseneural networks are further described in the above-incorporated U.S.Pat. Publication 20220128899, U.S. Pat. Application 17/992,870, U.S.Pat. Application 18/097,272, and U.S. Pat. Application 17/992,897. Asmentioned in these incorporated applications, some embodiments use oneMTN to generate all three contours instead of using three MTNs.

Also, each set of contours in the three different sets of contours insome embodiments corresponds to the predicted contours that would bemanufactured on an IC if the manufacturing process variation associatedwith that contour set is experienced. This is because the MTNs in theseembodiments are trained based on known contours (outputs) that areextracted from the manufactured ICs. In other embodiments, the threesets of contours are the contours that would be produced by the wafersimulation stage, as the MTNs are trained based on known outputsgenerated by a wafer simulator.

The input to the digital twins (e.g., MTNs 305-315) includes arasterized image of some shapes to be manufactured for a givensemiconductor layer. Pixel values range from 0 to 1, indicating thedegree of coverage of the area associated with the pixel. In someembodiments, gray scale values in between 0 and 1 are present for pixelscorresponding to the edges/corners of to-be-manufactured shapes. In someembodiments, these are shapes mostly likely to be interconnect shapes,e.g., metal layer interconnects. The output from the digital twincorresponds to an aerial image view (e.g., top-down view) of thecorrespondingly manufactured objects. In some embodiments, these areagain in the form of gray-scale images, from which the manufacturedshape contours are determined via a contouring operation. The contourswill be different from the originally drawn images, typically being insome curvilinear form as reflecting the physics of manufacturing.

FIG. 4 illustrates a process 400 for generating known input/output data(i.e., ground truth data) for training the digital twins. The process400 is a simulation process that is used in some embodiments to producean output training sample for a received input design training sample.In some embodiments, the input sample is an entire IC design, while inother embodiments, the input sample is a portion of an IC design in someembodiments.

When the input sample is the entire IC design or a large portion of theIC design, many input/output training pairs are extracted from the inputthat is supplied to the simulation process 400 and the output that isgenerated by this process. Under this approach, each extracted input isa particular smaller part of the IC design, while each extracted outputis the small part of the simulation process’ output that corresponds tothe particular smaller input part. On the other hand, when the process400 processes only small input design-layout samples to producecorresponding small wafer-simulation output samples, the process 400 isiteratively performed many times to produce many known input designlayout samples and the corresponding wafer-simulation output samples forthese input samples.

The process 400 in some embodiments generates series of imagesrepresentative of desired to-be-manufactured interconnect patterns.These are then simulated with semiconductor manufacturing simulationsoftware, under a variety of conditions. In some embodiments, the outputimages produced in response to the input images are further processed inorder to determine the images associated with the manufacturing processcorner extremes. In some embodiments, input, output pairs produced inthis manner are then used to train a digital twin, e.g., in the form ofa convolutional neural network. The process 400 incorporates the effectsof optical proximity correction (OPC) (including inverse lithographytechnology, ILT) as part of the overall manufacturing process as theseare accounted for to properly train the MTNs in some embodiments.

As shown, the process 400 starts by performing (at 405) a coloringoperation that separates an input sample into multiple mask layers. Inthe coloring operation, each feature of the input sample on a reticlelayer is colored to reflect the assignment of a feature to a particularmask layer. After the colorization operation, the process 400 performs(at 410) an OPC operation to produce one or more possible sets of maskdesigns, with each set of mask designs corresponding to the inputsample. OPC adds or subtracts patterns to a mask to enhance the layoutresolution and improve the printability or transfer of the mask patternsto the wafer.

For the input sample, the generated mask designs in some embodimentsinclude a nominal mask design with variation. In some embodiments, thepossible mask designs produced at 410 may be combined to create thenominal mask design with variations. Conventionally, the nominal maskdesign can be determined using a nominal dose, such as 1.0 andcalculating a nominal contour of a mask design at a threshold, such as0.5. In some embodiments, the nominal contour of the mask design iscalculated from several possible mask designs. In some embodiments, theOPC operation includes an ILT operation. The ILT operation in someembodiments creates ideal curvilinear ILT patterns, while in otherembodiments, the ILT operation rectilinearizes the curvilinear patterns.Instead of using advanced forms of OPC, including ILT, some embodimentsuse simpler forms of OPC, such as edge-based OPC, in which hammer heads,serifs, and line bias features are inserted. FIG. 5 illustrates examplesof edge/corner-based OPC patterns in which serifs 502, hammerheads 504and line biasing 506 are inserted.

After the OPC operation, the process 400 performs (at 415) a masksimulation operation to produce mask data preparation (MDP), whichprepares the mask design for a mask writer. This operation in someembodiments includes “fracturing” the data into trapezoids, rectangles,or triangles. This operation also includes in some embodiments MaskProcess Correction (MPC), which geometrically modifies the shapes and/orassigns dose to the shapes to make the resulting shapes on the maskcloser to the desired shape. MDP may use as input the possible maskdesigns or the results of MPC. MPC may be performed as part of afracturing or other MDP operation.

After the mask simulation, the process 400 performs (at 420) a wafersimulation operation that calculates possible IC patterns that wouldresult from using the generated masks. In some embodiments, the wafersimulation operation (at 420) includes a lithography simulation thatuses the calculated mask images. The operation at 420 calculates severalpossible patterns on the substrate from the plurality of mask images.After 420, the process ends.

For an input sample, the generated IC pattern in some embodimentsrepresents an output pattern or a range of output patterns (when theproduced shapes have multiple contours to account for process variationsand manufacturing parameter variations). The input sample and thegenerated output pattern represent a known input with a known outputthat are used to train the machine-trained neural network in someembodiments. Once trained, the neural network can then be used duringcompaction to assist in the routing operations of some embodiments.

It will be appreciated by those of ordinary skill that the process 400may be somewhat more, or less, involved than that shown. Typically, themask process simulation software can be parameterized i.e., instructedto perform the mask process simulation under a set of mask process(e.g., dosemap variation) parameter values. Likewise, the wafersimulation software can be parameterized i.e., instructed to perform thewafer process simulations under a set of wafer process (e.g., dosemapvariation and depth-of-focus variation) parameter values.

By adjusting such parameters, multiple output samples (e.g., multiplemanufactured contours) corresponding to multiple process variations forone input sample are produced in some embodiments. In this manner, thetrained digital twins of some embodiments can predict manufacturedshapes, while factoring both OPC and manufacturing process variations.By generating multiple input patterns by placing one input pattern in avariety of different neighboring variations with different neighboringpatterns, some embodiments also produce training data to account forneighborhood variations of any input pattern.

Some embodiments use the generated input/output training samples to putthe machine trained neural networks through learning processes thataccount for (1) manufacturing variations in one or more manufacturingparameters (such as dosage and focus depth) and/or (2) neighborhoodvariations that account for different possible components that neighborinput component patterns that are part of the inputs used for thelearning processes. To train the neural network, some embodiments feedeach known input sample through the neural network to generate anoutput, and then compare this generated output to the known output ofthe input to identify a set of one or more error values. The errorvalues for a group of known inputs/outputs are then used to compute aloss function, which is then back propagated through the neural networkto train the configurable parameters (e.g., the weight values) of theneural network. Once trained by processing a large number of knowninputs/outputs, the neural network can then be used to facilitaterouting operations of some embodiments.

To appreciate the benefits of digital twin MTNs, it is helpful tounderstand common issues experienced by most routers. In a typical EDAflow, routing is often performed after Clock Tree Synthesis (CTS) andoptimization, and results in the exact interconnect by which macros,standard cells, and I/O pins are connected. The interconnect is realizedvia metal tracks and inter-layer vias in the layout, which often followsthe same logical connections present in the pre-routed netlist. Afterthe CTS step, the router has access to information including the variouscell placements, any blockages which routing must avoid, the variousclock tree buffers/inverters inserted during CTS, and of course the I/Opins themselves.

This information steers the router to electrically complete allconnections defined in the netlist. Routers are often guided byconstraints such as (1) the number of interconnect layers to be used,(2) the maximum length for the routed interconnect wires, (3) theminimum width of, and minimum spacing between, the interconnect wires,(4) routing mostly along preferred routing directions often includinghorizontal and vertical (specific layers are to be routed in particulardirections only or primarily), (5) off-grid routing constraints, (6),blockages (predefined areas which block routing in particular areas),(7) allowed routing areas, which limit routing to specific areas only,(8) routing region precedence, (9) routing density, (10) pin connectionconstraints and (11) restrictions in how much rerouting can take place.

Routers try to ensure that (1) any DRC violations introduced duringrouting are minimized, (2) routing is completed, i.e., the design is100% routed with minimal discrepancies between the post-routed layoutand the pre-routed netlist, (3) Signal Integrity (SI) related violations(such as cross talk, delta-delays, etc.) are minimized, (4) congestionhotspots are eliminated or minimized, (5) timing goals are accomplished,specifically, the Quality Of Results (QOR) of the timing is sufficientlygood (e.g., sufficiently high clock speeds are attained), and timingcheck violations (e.g., setup and hold violations, etc.) are eliminated,(6) goals are accomplished in the face of ever increasing manufacturingvariations, specifically, manufacturing repeatability is maximized,which is a challenge particularly for smaller geometry processes, and/or(7) reliability-related sub-goals are accomplished (such as metaldensity is correct, antenna effects are eliminated/minimized,electromigration effects are minimized, etc.).

The various routing goals and constraints are often conflicting, andachieving a routing solution that eliminates all issues, and has fullyachieved all goals, is often an intractable problem. The long list ofoften conflicting objectives is what makes routing extremely difficult.Due to the extremely high compute time to best meet these conflictingobjectives, routers therefore seldom attempt to find an optimum result.Instead, almost all routing is based on heuristics which try to find asolution that is good enough.

As a result of these heuristics, many existing routers (1) createsolutions that require more routing layers than actually needed, withthe corresponding extra mask sets adding to the manufacturing cost, (2)create solutions with sub-optimal timing (or at least, less-optimal thanwould otherwise be attained should more precise models of resistance andcapacitance and their impacts of timing have been available), (3) createrouted designs that increase via count (and so resistance increases),(4) create more complex routing solutions than actually needed tominimize crosstalk, (5) create routed designs that are difficult tomanufacture in terms of printability, increasing the burden ondownstream OPC tools and (6) abandon a tentative routing solution as‘infeasible’, when in fact it is feasible. All of these issues cannegatively impact the time for the router to find a good enoughsolution, or can result in a solution with inadequate quality ofresults.

EDA tools often use a two-stage approach to make the solving of thecomplex combinatorial problem of routing more manageable. The two stagesare global routing and detailed routing. Global routing first dividesthe area to be routed into relatively large tiles, and determines thetile-to-tile paths for all nets. During the determination of thetile-to-tile paths, the global router also seeks to optimize anobjective function, such as a function related to total wire length, andcircuit timing. After the global routing has identified the tile-to-tilepaths, the detailed router typically performs the actual track and viaassignment for the various nets in the tiles.

FIG. 6 illustrates an example of global and detailed routing that definefirst a global route and then a detailed route to connect two pins 600and 601. This example is illustrated in three stages 610, 615, and 620.In the first stage 610, the routing area is first partitioned by theglobal router into four square cells such that the two pins are locatedin the top-left and bottom-right squares respectively. The global routerproduces the global route 602, in which the dashed line traverses thethree cells involved in the routing solution (top-left, top-right, andbottom-right). The bottom-left cell is ignored by the global routingsolution in this case.

The second and third stages 615 and 620 illustrate the detailed routingprocess. The second stage 615 shows the grid lines that the detailedrouter defines in the three cells that contain the identified globalroute 602. In the grid defined by these grid lines, the detailed routerthen defines the detailed route 604. As shown, this detailed route 604has three segments that are assigned to the grid lines, which correspondto metal tracks on wiring layers. The darker segments run on thehorizontally routed nth metal layer, while the lighter vertical segmentrun on the vertically routed metal n+1 layer, with vias 608 inserted atthe appropriate transitions between the two layers.

For global and detailed routing problems that are expressed in terms ofgraph problems, a graph-searching technique is often applied to solveeach problem. Popular graph-searching techniques include maze processes,line-search processes, and the A* search process. These processes aregeneral-purpose as they are applied to both global routing and detailedrouting, though specializations often apply. These graph based processesare often guided by congestion and timing information. This informationin turn is associated with routing topologies and routing regions. Inorder to minimize congestion, and to balance net distribution amongrouting regions, routers assign larger costs to route nets throughregions of high congestion. Modeling the routing resource as a graph,where the graph topology represents the chip structure, allows thegraph-search technique to be deployed.

In global routing, the rectangular tiles that are used to divide therouted area (e.g., the chip) are called global routing tiles (orgCells), each of which accommodate dozens of routing tracks in eachdimension. A node in the graph represents a tile or gCell on the chip,and edges represent the boundaries between two adjacent tiles/gCells.Each edge is assigned a capacity based on the physical area availablefor routing, or in more modern approaches, depending on the number oftracks in the tile.

Global routers find tile-to-tile paths for all nets on the globalrouting graph described above. These paths in turn guide the detailedrouters. The overarching goal for the global router is to route as manynets as possible while meeting the capacity requirements of each globalgraph edge, along with any other constraints that are specified. Forrouters with a timing-driven focus, extra costs are typically added tothe routing topologies which incur longer critical path delays. Afterglobal routing, detailed routers determine the actual physicalinterconnections of nets via the allocation of wiring on specific metallayers, and the use of between-layer vias to switch between theselayers.

Two common layer models are used, which are often denoted reserved andunreserved layer models (also called preferred and non-preferred wiringdirection models). In the former, each layer is only allowed to run, orstrongly biased to run, in one specific routing direction (e.g., allwires in that layer must run horizontally, or all wires must runvertically). The direction is known as the preferred routing direction.In the unreserved model, wires are allowed to run in any direction,e.g., horizontally or vertically within the same layer, or in eightdirections within the same layer. It is common in many routers to usethe reserved model, i.e., preferred direction routing, due to its lowerproblem complexity, and its tendency towards improved manufacturability,e.g., due to semiconductor manufacturing, lithography systems often usespecific light sources which are optimized for one direction or theother, but not both.

Two primary routing models have been used to date for detailed routing.These are gridless routing models and grid-based routing (also calledshape-based routing). In the former, a grid is superimposed on therouting area, and routing paths within the grid are then found by thedetailed router. The latter refers to any other kind of model, i.e.,models that are not strictly grid based.

FIG. 7 illustrates two examples that illustrate the grid-based andgridless models. In a gridded routing model 702, a routing grid 705 issuperimposed on the routing area, and the detailed router is constrainedto finding routing paths that adhere to that grid. In other words,grid-based routers superimpose a fixed grid on the routing area, findingrouting points within, and only within, the grid. The space betweenadjacent lines on the grid is called the wire pitch. Wire pitches aredefined in the technology file, and are greater than or equal to thecombined minimum spacing and minimum width of the wires for the layer.

When the detailed grid-based router uses preferred direction wiring, thesearch space is constrained such that the wires on any layer run only inthe preferred direction (e.g., horizontal or vertical direction) on thatlayer, or are strongly biased to run along the preferred direction. Inthis model, vias 715 that allow routes to change layer are performed atthe intersection of the horizontal and vertical grid lines. Further,minimized-width wires that follow the legal paths in the grid usuallysatisfy the design rules by construction. In combination, this greatlyreduces the search space compared to the gridless model, makinggrid-based routing models more computationally efficient, though at thecost of reduced flexibility.

Gridless routing model 704, on the other hand, does not have these gridenforcements. By not following a pre-defined routing grid, the gridlessdetailed routers allow different wire widths and different wirespacings, which in turn, provides greater flexibility in finding arouting solution. Because the wire widths and spacings are not as highlyconstrained as those of the grid-based router, the gridless router ismore suitable for optimizing or tuning interconnects, e.g., byperforming wire sizing and perturbation. However, due to the highercomplexity, gridless routing models tend to have higher computationalcosts than grid-based models and are often slower than the grid-basedapproach.

Given a ‘high level roadmap’ produced by a global router, a detailedrouter has the task of identifying the exact tracks and vias to be usedwhen routing nets. By limiting the detailed router to the tilesidentified by the global router for each net, the overall search spacecan be drastically pruned and the overall routing time correspondinglyreduced. For older process nodes, with large geometries and relativelyfew metal layers (e.g., 3 layers of metal only), wires are mostly routedin the free space between blocks. For example, for a standard cell baseddesign, the routing is performed in spaces between the standard cellrows. For newer nodes, with smaller geometries and a relatively largenumber of metal layers (e.g., up to 11 metal layers for today’snanometer-scale processes), routing is done in the metal layers abovethe cells/blocks. This is known as over-the-cell routing. This approachis also used for full-chip routing.

Routing approaches need to meet various constraints in addition tomerely completing the routing of a design. These constraints include twomajor types, which are performance constraints and design constraints.Performance constraints are to ensure the connections result in chipperformance specifications provided by the designers. Circuit timing istypically the most important performance constraint, but powerconstraints and area constraints (the collective then referred to asPPA, or Performance, Power and Area) are also common.

Design rule constraints tend to relate to manufacturability, and areprovided by the foundry rather than the chip designer. These constraintsare often provided in the form of design rules, such as minimum wirewidth, minimum wire-to-wire spacing, or via-to-via spacing. Other commonrules include overlap or extension rules, by which for example a wireend must overlap or extend beyond a via by some minimum amount.

FIG. 8 illustrates examples of three types of design rules that areoften checked. These design rules are component width rule thatspecifies the minimum width of a component, a component spacing rulethat specifies the minimum spacing between two components, and anenclosure spacing rule that specifies the minimum spacing for one object(e.g., one metal contact on one layer) to overlap another object (e.g.,another metal object on another layer).

As mentioned above, routers often employ rip-up and reroute strategies.An initial net ordering is assumed and nets are ripped up and re-routedas needed to meet constraints. Some common net ordering schemes include(1) ordering the nets in ascending order based upon the number of pinswithin their bounding boxes (nets with larger pin counts tend to blockother nets within this bounding box), (2) for timing performance-drivenrouters, ordering the nets in descending order of their lengths (longernets should be routed first for high performance designs, as theytypically dominate the overall timing), (3) for routability-drivenrouters (find a routing solution at all costs), ordering the nets inascending order of their lengths (routing shorter nets first leads tobetter results, as these nets tend to have less flexibility than thosefor longer nets), and (4) ordering the nets in terms of their timingcriticality. In some cases, nets in congested regions are often routedbefore nets in less congested regions.

Rip-up and reroute include identifying bottleneck areas and ripping upsome of the nets which have already been routed, routing the nets whichhave previously been blocked and then rerouting the ripped upconnections. Rip-up and reroute is often an iterative process, runninguntil all nets are successfully re-routed or a time limit/iterationcount is exceeded, and often leads to improved routing solutions.

For newer nodes, with small geometries and a relatively large number ofmetal layers (e.g., up to 11 metal layers for today’s nanometer-scaleprocesses), routing is done ‘over-the-cell’ in the metal layers abovethe cells/block. The full chip routing problem is very complex andrepresents a large combinatorial problem. To increase tractability,various divide-and-conquer approaches are used. As mentioned above, onedivide-and-conquer approach is the two stage technique of first runninga global router to arrive at a very coarse routing using gCells, whichis then refined via a detailed router (within one or multiple gCells).In order to gain even more tractability on larger problems however, itis commonplace to transform the problem into smaller problems which arethen divided into even smaller sub-problems. The router then proceeds ina top-down manner, a bottom-up manner, or a hybrid manner (combiningboth approaches). At each problem level, the nets can be routedsequentially or concurrently (e.g., by using a solver).

FIG. 9 illustrates an example of a top-down manner, a level by levelapproach for routing a 3-pin net. In this example, four successive gridsare used for four successive levels, starting with level 3 and endingwith level 0. Each of the higher levels uses a coarser grid than thelevels below it. At each higher level, a coarser route is defined byreference to the coarser grid of that level, until the route for level 0is defined. At each particular level 2, 1, or 0, the route that isdefined respectively for level 3, 2, or 1 is used as the starting inputto define the route at that particular level.

A limitation of this hierarchical approach is that the routing decisionsmade at a given hierarchical level are not always optimal for subsequentlevels. Therefore, in a hybrid approach that combines boundedmaze-routing processes with both top-down and bottom-up approachesalleviates this problem. FIG. 10 illustrates an example of a hybridhierarchical approach 1000 to routing. This approach (1) maps at 1002pins and blockages up one level (lower resolution grid) to find a pathat the upper level, (2) maps at 1004 the upper level connections backdown to the lower level (higher resolution grid) to form preferredregions, and (3) finds at 1006 a solution within the preferred regionson the lower level.

The approach has three-phases including neighboring propagation,preference partitioning, and bounded routing. The first phase attemptsto perform a wave propagation from each pin using a bounded maze routingprocess to propagate W circles of waves, where W is a user-definedparameter. If that fails, the second phase recursively maps the pins androuting blockage/obstruction areas onto the next adjacent upper level,i.e., a lower-resolution grid, repeating the recursive operation until asolution path is determined. The resulting low-resolution path is thenmapped back onto the high-resolution grid in the third phase, formingpreferred regions and those preferred regions are used to constrain thesearch space in the determination of the final routing path.

Some embodiments combine the hierarchical approach with a convolutionalneural network in the first phase, i.e. for failed nets, to map (e.g.,at 1002) the pins and blockages up one level to a lower resolution grid,and then use the CNN for finding a path at that upper level. Here, theconvolutional neural network is used to solve the higher level routingproblem, the solution of which is then mapped down to form the preferredregions for the lower level. In some such embodiments, the neuralnetwork only knows about the upper level problem, but does not know muchor anything about the lower level problem.

In other embodiments, the CNN is used at the lower and higher levels,e.g., the network performs both the higher level mapping, route solving,and re-mapping back to the lower level as preferred areas. Under thisapproach, the CNN is aware of one or both hierarchical levels, and alsodoes one or both of the up/down mapping operations.

Some embodiments use deep reinforcement learning in lieu of the mazerouting or other traditional routing approaches at any of thehierarchical levels. In some embodiments, a deep reinforcement agent isused to route each net sequentially, or a ‘team’ of deep reinforcementagents are used to route nets concurrently, following the Multiple-AgentReinforcement Learning (MARL) paradigm.

During the routing of the lowermost hierarchical levels (within thepreferred areas), DRL is used in combination with a front-to-backdigital twin in some embodiments. In some embodiments, a digital twinMTN is used within the reward function for the reinforcement learning,taking the actual manufactured contours that correspond to as-routedcandidate solutions into account, and penalizing those which willmanufacture poorly. The penalty component as part of the reward functionwill serve to guide the agent to produce final lowest-level routingsolutions that provide the most manufacturability.

FIG. 11 illustrates an example of another common multi-level approachknown as A-shaped (Gamma) multi-level routing. As shown, the routingarea is divided into an array of rectangular subregions, known as globalcells. Each global cell contains dozens of routing tracks in eachdimension. A node in the routing graph corresponds to a global cell, andan edge represents the boundary between two cells. Each edge is assigneda capacity. The approach is repeated at multiple hierarchical levels(e.g., the lowest level is G0, the level above that is G1, then G2,etc.). Routing then has a bottom-up coarsening, followed by a top-downun-coarsening or refinement. Coarsening is a bottom-up approach thatiteratively groups a number of global cells, starting from the finest(bottom) level, and merging 4 adjacent global cells into a ‘coarser’cell at the next level up. Resource estimation is then performed for thecoarser cell at that next level up.

The coarsening process repeats this operation in an iterative, upwarddirection until the number of cells at the top level is less than someminimum threshold. Un-coarsening proceeds in the opposite direction,again in an iterative manner. This time, starting from the top, a globalcell is decomposed into 4 smaller cells at the level below, each ofwhich is further decomposed into 4 smaller cells at the level belowthat, etc. The process continues until the ‘bottom’ is reached, i.e.,the finest level of granularity is reached.

The process first applies a minimum spanning tree (MST) process todecompose each net into 2-pin connections. Global routing is firstperformed for the local 2-pin connections at each level of thecoarsening stage, and then the detailed router is used to determine theexact wiring. Local 2-pin connections are those that sit entirely withinthe global cell at a given level. Non-local connections (that spanmultiple global cells at a given hierarchical level) are deferred untila higher hierarchical level is reached.

During the detailed routing, a cost function is used to control thecongestion, and the global routing process always searches for theshortest global routing path between two pins in order to minimize thewire length. After the global routing is completed for a givenhierarchical level, a detailed routing step is applied for the samelevel. In this step, the process simultaneously minimizes path lengthand via count, e.g., by using a maze-routing process. This process findsthe shortest path with the minimum number of wire bends and vias,usually with an emphasis on the via count due to the high resistance ofvias. Since the global and detailed routing steps are effectivelycombined together at each hierarchical level, along with resourceestimation, the resulting resource estimation is more accurate. Thisfacilitates refinement of the routing solution using rip-up and rerouteduring the subsequent refinement/un-coarsening stage.

For the gamma multi-level routing approach of FIG. 11 , some embodimentsuse a CNN to replace the maze routing process at any given hierarchicallevel. Other embodiments use CNNs to replace maze routing at somehierarchical levels, while continuing to use the maze routing processesat the other levels. Some embodiments use deep reinforcement learning toreplace the maze routing process at any given hierarchical level. Otherembodiments use deep reinforcement learning to replace maze routing atsome hierarchical levels, while continuing to use the maze routingprocesses at the other levels.

Some embodiments use both CNNs to perform the routing (viaimage-to-image translation), and deep reinforcement learning, inconjunction with, or to replace, any of the maze routing steps at any ofthe hierarchical level. Further, the introduction of the front-to-backdigital twin (which understands the exact shapes that can bemanufactured) is used to perform manufacturability-aware routing at anylevel, but particularly at the lowest level G0. For the deepreinforcement learning cases, some embodiments incorporate thefront-to-back digital twin into the reward function.

While track and layer assignments are often performed by the detailedrouter after the global router has finished, this is not always thecase. For example, some have proposed a global router that performsdelay-driven layer assignment under a multi-tier interconnect structure,considering the fact that higher layers of metal lead to fatter wireswith smaller resistance. A two-stage process first minimizes the totalwire delay, and via count simultaneously by a dynamic programming andnegotiation technique, and then further minimizes the maximum delaycarefully while not increasing the via count.

This approach reduces the total delay and maximum delay while keepingroughly the same via count, compared with state-of-the-artvia-count-minimization methods. The approach also benefits from theobservation that thicker interconnects on higher layers lead to lowerresistance/fatter wires, which has a large impact on the interconnectdelay, and so the delays incurred by layer assignment need to becarefully considered. The approach transforms a 2-D global routingproblem solution into a 3-D multi-layer solution in which delays and viacount are minimized, subject to wire congestion constraints.

For such an approach, resistances and capacitances of the metal wiresand vias are accounted for by using a 3-D RC model. FIG. 12 illustratesone manner of accounting for the contribution of RC segment by computingan Elmore delay at a sink. As shown, the distributed Elmore delay modelis adopted to estimate the interconnect delay, such that the delay of anet T is a weighted sum of the segment resistance R_(s) times half thesegment self-capacitance C_(s) plus the load capacitance C₁. A firststage uses a layer assignment process for simultaneous delay and viacount minimization (SDLA), which is based on a dynamic programmingtechnique, in order to find a 3-D layer assignment of a 2-D routed net,such that the minimum total cost of the delay, via account and wirecongestion is minimized.

The second stage further minimizes the maximum delay while notincreasing the via count. Below is the pseudo code for a process thatimplements the second stage.

     1. initialize PriorityQueue Q by nets’ delay and set Flag←true     2. while Flag do     3.    get net T with maximum delay D_(T) in Q and its 3D pathP_(T)     4.    rip-up-and-re-assign T by SDLA with large λ and without consideration of the wire           congestion, get the new delay D′_(T)     5.    if D′_(T) ≥ D_(T) then recover old path P_(T )to T and break end if     6.    traverse the new path of T and get the candidate net set S     7.    foreach net T1 ∈ S in the decreased order of net delay do     8.       backup old path P_(T1) of T1     9.       rip-up-and-re-assign T1 by SDLA with large λ under the wire congestion              constraint, get the new delay D′_(T1)     10.      if D′_(T1) ≥ D_(T )then     11.          recover old path P_(T1 )to T1     12.            rip-up-and-re-assign T by SDLA with large λ under the wire congestion                    constraint, get the new delay D″_(T)     13.          if D″_(T) ≥ D_(T )then Flag←false end if     14.          break      15.          end if     16.       end foreach     17.       update Q by T and T1’s with corresponding new delays     18. end while

The performance of the above-described processes are dependent on theaccuracy of the segment delays. Segment delays are dependent on thevalues of the segment resistances R_(s) and capacitances C_(s), which inturn depend on the actual shapes as manufactured. Hence, to computeaccurate resistance, capacitance and delay computations, someembodiments use the digital twin neural network to produce the predictedcurvilinear manufactured shapes, such as the shapes illustrated in theabove-described FIG. 2 .

U.S. Pat. Publication 20220128899, U.S. Pat. Application 17/992,870,U.S. Pat. Application 18/097,272, and U.S. Pat. Application 17/992,897describe how some embodiments use convolutional neural networks (CNNs)as digital twin processes that produce the predicted manufactured shapesunder process variations. The CNNs that are described in theseapplications are both accurate and fast due to the ability of the CNNsto leverage the computational resources of devices such as GraphicsProcessing Units (GPUs) or Tensor Processing Units (TPUs), etc. Toproduce the predicted manufactured shapes, these CNNs are trained withoutput shapes that are manufactured on ICs from input IC design layoutshapes in some embodiments. In other embodiments, the CNNs are trainedwith output shapes that are produced by wafer simulation processes frominput IC design layout shapes, as described above by reference to FIG. 4. Such differing training techniques are further described in theabove-incorporated applications.

By using the manufactured shapes and their precise tolerances, someembodiments compute extremely accurate parasitics R_(s) and C_(s) forthe wire network. Some of these embodiments compute the parasiticsaccurately via a 3-D electromagnetic solver, while other embodiments usea second digital twin (in place of slower solvers) to rapidly calculatethe parasitics. U.S. Pat. Publication 20230027655 describes these twodiffering techniques for computing parasitics. U.S. Pat. Publication20230027655 is incorporated herein by reference.

Some embodiments use the more accurate resistance and capacitance valuesthat are produced in conjunction with digital twins, or by digitaltwins, to estimate the interconnect delay (e.g., through the use ofthese values in distributed Elmore models) during routing. In someembodiments, the interconnect delay is used within a process thatsimultaneously minimizes delay and via count. This process in someembodiments is used to perform delay-driven layer assignment in globalrouting, e.g., under multi-connect interconnect structures. In someembodiments, the use of the more accurate parasitics leads to routesbeing assigned to different layers, which can have drastically differentelectrical characteristics, and thereby have a large positive impact onthe quality of results of the routing solution.

Some embodiments also use digital twins to quickly and accuratelypredict parasitics and then produce more accurate interconnect delays(e.g., Elmore delays) based on these parasitics, in order to improve theperformance of a process that minimizes the maximum delay. The processescited are exemplary, and not intended to be limiting. It will beappreciated by those of ordinary skill that other processes are used inaddition to, or in place of, the processes described here, to improvelayer assignments during routing, based on the use of digital twins forimproved parasitic estimates.

As device geometries have shrunk in modern processes, wire heights havegrown taller, and the spacings between wires have decreased, therebyincreasing coupling capacitance between wires. The coupling capacitancenow exceeds self-capacitance and forms a substantial portion of thetotal capacitance. The increased capacitive coupling between wires hasin turn become a key issue for signal integrity in terms of creatingunwanted crosstalk. Signal integrity noise comes in two flavors. Oneintroduces a malfunction in a chip, inverting the logic values of gates,and the other presents itself as timing changes.

FIG. 13 illustrates an example of a crosstalk effect, a main source ofnoise. As shown, a pulse on an active Wire 1 induces a smaller pulse onthe passive Wire 2, which is capacitively coupled to wire 1 via couplingcapacitance Cc. The bigger the coupling, the bigger the effect on thepassive net (also called the victim net). Crosstalk is mostly related tocoupling capacitance on same-layer nets. Crosstalk is proportional tothe coupling of two wires on the same layer. This coupling is determinedby the relative positions of the wires. Coupling capacitance between twoperpendicular wires is minimal, while coupling capacitance between twoparallel, closely spaced wires can be quite large. Crossover andcrossunder capacitances to the wires on the interconnect layers aboveand below are also small in comparison to the lateral coupling on thesame-layer wires. Coupling between two parallel same-layer wires isproportional to the overlapping interconnect length, and inverselyproportional (though in a non-linear manner) to the distance betweenthem, increasing significantly as the distance gets too close.Crosstalk-aware routers therefore have to minimize the overlapping runlength between closely adjacent wires or ensure that wires which mustrun in parallel are sufficiently spaced apart (e.g., not on adjacenttracks).

FIG. 14 illustrates an example of an intermediate stage in A-shaped(Gamma) multi-level routing that minimizes crosstalk. In this routing, alayer/track assignment heuristic is used to minimize crosstalk in theintermediate stage of the A-shaped (Gamma) multi-level routing.Layers/tracks are assigned at an intermediate stage 1405 between thelast coarsening step 1410 and the first un-coarsening step 1415 of themultilevel framework. Long interconnect segments are carefully assignedto layers/tracks in the intermediate stage 1405, so as to attempt tominimize parallel run length on adjacent tracks, and so minimizecrosstalk.

FIG. 15 illustrates an example of a track assignment problem forcrosstalk minimization in which 6 wire segments a-f are to be assignedto tracks 1-4, in the presence of some blockages 1505 and 1510. The goalis to assign the 6 net segments to the different tracks, whileminimizing the parallel run lengths for the segments on adjacent tracks.FIG. 16 illustrates an example of a potential solution to acrosstalk-aware track assignment problem. As shown, the longest wiresegment ‘b’ has been assigned to the first track, which also has roomfor the short segment ‘a’. Medium-short segments ‘c’ and ‘f’ have beenassigned to the second track in such a way that the parallel run lengthbetween both of them and segment ‘b’ is reasonably small. The secondlongest segment ‘d’ is assigned to the furthest away track (track 4)from the track containing the longest segment ‘b’. Segments ‘c’ and ‘e’are similar in length and can be interchanged.

Typical crosstalk-aware track assignment processes assume that the wireswill be manufactured as perfect rectangles and do not factor invariations in the spacing, wire bulging, pinching or other effectsrelated to fine-geometry lithography, even in the presence of OPC/ILT.These non-idealities in wire manufacturing of course have an impact onthe coupling capacitance. Accordingly, some embodiments use a digitaltwin MTN to generate the predicted manufactured shapes, and then usethese shapes to identify the crosstalk-minimization track assignmentsolution.

With the knowledge of the expected manufactured shapes, the actualcoupling capacitance between the shapes is more accurately determinedrather than simply estimated from a simple capacitance model assumingwires are manufactured in perfect rectilinear form as produced by thedesign layout tool. This more accurate determination can then be used tofine tune the track assignment results. In other words, by using digitaltwins, some embodiments consider other combinations than the onedescribed above. For example, after using digital twin CNN to producethe expected manufactured shapes, some embodiments would explore acombination where wires ‘c’ and ‘e’ are interchanged, or a combinationwhere wire ‘c’ is moved further to the left or right, to avoid theimpact of the blockage on its manufactured contours and hence itscoupling capacitance to wire ‘b’. Even a small change in placement/trackassignment in some embodiments result in a significant difference tocoupling capacitance (and hence crosstalk) for particularly sensitivenets. The accurate capacitance values in some embodiments are thereforeused in more intelligent decision making.

One way to determine the more accurate coupling capacitance is to run anEM solver on the predicted manufactured shape contours produced by thedigital twin MTN, particularly those for the outer contour correspondingto one manufacturing process parameter extreme. This however, can be tooslow to be used for routing operations in some cases. Accordingly, someembodiments use a faster way of computing the coupling capacitance byusing a digital twin neural network that extracts coupling-capacitanceextraction instead of the solver. In some such embodiments, one digitaltwin MTN produces the predicted manufactured shapes while a seconddigital twin MTN computes the curvilinear coupling capacitances. Underthis approach, the intermediate curvilinear as-manufactured shapes areexplicitly inferred and considered during the capacitance computationoperation of the second digital twin.

The curvilinear coupling-capacitance extraction digital twin is trainedwith images corresponding to known manufactured curvilinear shapes asinput samples and these input shapes’ corresponding coupling capacitanceas output samples. To generate these input/output sample pairs (i.e.,the training data), some embodiments use a field solver that receivescurvilinear-shaped 3-D conductor input structures (i.e., each inputsample) and that produces corresponding capacitive coupling outputsamples for each received input structure. For each input structure, thefield solver produces the coupling capacitance output by solving theelectromagnetic equations for the input structure. In this case, atcapacitance-inference time, the front-to-back digital twin is first usedto explicitly compute the predicted manufactured wire shape images, andthen these are directly consumed by a second network which computes thecapacitance values.

In other embodiments, the two networks (i.e., the network that producesthe predicted manufactured shapes and the one that computes thecapacitive coupling for the shape) are combined into a single network.In some of these embodiments, the input to this single network includesa raster image of the routing solution (e.g., the rectilinear trackassignment candidate solution) and its neighboring structures, and theoutput comprises the corresponding parasitic values (e.g., parasiticcapacitance values) for the corresponding parasitic coupling on therouting solution from its neighboring structures.

The predicted manufactured wire contours are not explicitly computed,but rather implicitly computed in some abstract form within the model.Such a model would be trained by generating the data in two stages.First, the front-to-back digital twin is used to explicitly compute theimages containing the predicted manufactured wire shapes pertaining to atrack assignment candidate solution, and then an EM solver (orcurvilinear parasitic extraction digital twin) is used to consume thoseimages and produce the capacitance values. The initial image pertainingto a track assignment candidate solution and the final capacitancevalues are then used as a known input/output pair to directly train thenetwork, along with many other input/output pairs that are similarlygenerated.

In some embodiments, the front-to-back and/or capacitance-extractiondigital twins is used in the reward function of a RL (reinforcementlearning) approach to detailed routing. By incorporating either or bothof these digital twins into the reward computations for a DRL (deepreinforcement learning) approach to detailed routing, the DRL agent insome embodiments are crosstalk-aware and guided to produce detailedrouting solutions that minimize crosstalk. DRL approaches are furtherdescribed below.

In some embodiments, a parasitic extraction digital twin predicts, veryquickly, and with a high degree of accuracy, values for the parasiticelements associated with semiconductor interconnect. Further, in someembodiments, it predicts these parasitic values reflective ofmanufacturing process variations, including nominal case, best case andworst case values. Examples of parasitic values include capacitance andresistance. In some embodiments, the parasitic extraction digital twinis implemented in the form of a neural network.

In some embodiments, the parasitic extracting MTN accepts multipleinputs (or a single input with multiple layers, analogous to RGB layersin a color image), and outputs one or more parasitic values. The inputscorrespond to rasterized images associated with different semiconductorlayers, e.g., different metal layers, via layers, or some combination.The outputs correspond to parasitic values, e.g., capacitance values,associated with the different conductor shapes represented in the inputimages.

FIG. 17 illustrates an example of a capacitance matrix between a shape(middle, middle) and other shapes, in which three semiconductor layers(metal 1, via 1_2, and metal 2) are represented. Each figure containsthree (white colored) shapes, assumed to be three different electricalsemiconductors. Nine different electrical semiconductors are present.The metal 2 layer 1702, contains three closely-spaced (white colored)shapes, two of which are rectangular (left, right), and one of which isa diagonal. The via_1_2 layer 1704 also contains three shapes. Theleftmost of these, however, is spaced fairly distantly from the middleone, whereas the rightmost is again spaced fairly closely to the middleone. The left and right shapes on the via layer are rectangular, and themiddle shape is a diagonal shape.

On the bottom ‘metal 1’ layer 1706, there are again three shapes, withmedium spacing. On this layer, there are also two rectangular shapes anda diagonal shape in the center. Each of these white shapes representssome semiconductor material on a semiconductor wafer layer. White colorpixels indicate where semiconductor material (e.g., metal) is present,and black color pixels indicate where the semiconductor material isabsent.

The capacitance matrix 1700 includes nine numbered arrows (1 through 9),and the capacitance table 1705 on the right contains some labels (e.g.,left, middle, etc.) corresponding to these arrows. The capacitance table1705 represents nine key capacitance values of interest, all of whichinvolve the middle shape on the via layer 1704 (i.e., the diagonal shapeon the middle ‘via_1_2’ layer 1704, from which all arrows emanate), toall nine semiconductor shapes (one arrow (5) of which represents aself-capacitance, from the (middle, middle) diagonal shape to itself).

FIG. 18 illustrates that in some embodiments a neural network 1805 istrained and used to infer the nine capacitance values for the ninecapacitive couplings on the middle shape of the via layer 1704. Theabove-incorporated U.S. Pat. Publication 20230027655 describes thetraining of this network, as well as the use of this network to generatematrices of capacitance values like the matrix 1700 of FIGS. 17 and 18 .As described above and as described further in this incorporated patentapplication, some embodiments then use the capacitance values from thecapacitance matrix 1700 to solve a set of one or more equations thatcompute a parasitic capacitance value to express the parasitic effectexperienced by the middle shape of the via layer 1704. This parasiticvalue expresses the parasitic capacitance effect on this middle shape byitself and its neighboring structures.

As mentioned above, a parasitic extraction neural network in someembodiments is trained to produce a single output parasitic capacitancevalue instead of a capacitance matrix such as the one illustrated inFIGS. 17 and 18 . This parasitic value expresses the parasiticcapacitance effect on this middle shape by itself and its neighboringstructures.

Alternatively, parasitic extraction neural network in some embodimentsis trained to produce a single output parasitic capacitance value thatexpresses the parasitic effect of just one neighboring structure at atime. FIG. 19 illustrates an example of such a neural network 1900. Asshown, a 6-channel image is input to the neural network 1900. The firstthree channels are used to describe the full context for the parasiticextraction that expresses the capacitances on the oval shaped conductor1920 on metal layer 2. For this oval shaped conductor, these threechannels include all the neighboring conductors on the same metal layeras well as on the metal layer above and below a conductor whosecapacitances are to be extracted.

Additionally, three more channels are used to present a mask, indicatingin a graphical form which particular conductor is of interest, i.e.,which specific conductor’s coupling capacitance to the primary conductor(center conductor on the center metal layer) is to be determined. In thethree mask channels, only a single conductor (corresponding to one ofthe multiple conductors in the vicinity) is represented. Further, theneural network now produces a single output value, rather than the 9values described previously. This single value is the capacitivecoupling on the oval shaped conductor by the object 1925 on the thirdmetal layer that is identified by three masks.

This general approach allows for any number of contextual conductors tobe present in the area surrounding the primary conductor of interest(e.g., the center conductor of the center metal layer). All contextualconductors are accounted for in the first three channels, while theadditional mask channel images indicate which of these is to beconsidered. All contextual conductors need to be included forcapacitance prediction, as the addition or subtraction of any one ofthem changes the capacitances for all of the remaining conductors. Thisapproach is used in some embodiments that use a trackless router.

Instead of producing matrices that include parasitic values (e.g.,capacitance values) computed by the MTN, the MTN of some embodimentsproduces parasitic parameters from which the parasitic extraction toolcan compute parasitic values. For instance, as described in theabove-incorporated U.S. Pat. Publication 20230027655, the MTN of someembodiments outputs parasitic capacitances per unit length. Theparasitic extraction tool then identifies the overlapping length betweentwo adjacent conductors and multiplies this length by the capacitanceper unit length to compute the parasitic capacitive coupling by one ofthese conductors on the other.

FIG. 20 illustrates a process 2000 that uses a digital twin MTN duringrouting to identify routes with acceptable parasitics. In someembodiments, a router uses the process 2000 repeatedly during routing togenerate routes. As shown, the process 2000 initially identifies (at2005) a set of one or more routes for a set of nets in a design layoutby using one or more conventional routing processes. In someembodiments, a router uses the process 2000 for each route that itdefines for each net, while in other embodiments, the router uses theprocess 2000 for a group of routes that it defines for a group of nets(e.g., as part of a rip-up-and-reroute operation). To define each route,the process 2000 uses (at 2005) one of the traditional detailed routingprocesses that are commonly used today to define detailed routes.

Next, at 2010, the process uses the digital twin MTN to identifyparasitic effects on (e.g., parasitic capacitances experienced by) theset of routes identified at 2005. To use the digital twin MTN, theprocess 2000 in some embodiments rasterizes (i.e., pixelates) the designlayout portion that contains the identified set of routes, and suppliesthis rasterized representation to the digital twin MTN. When the routerdefines its routes in the contour domain, the process 2000 firstperforms a rasterization operation that transforms the contour/geometricdefinition of the design layout into the pixel-domain in which theshapes in the design layout are represented by actual pixel values,e.g., such as those described above. For process 2000 and otherprocesses described in this document, different embodiments usedifferent known rasterization processes to transform the contourdefinition of a design into the pixel domain.

In some embodiments, the MTN processes the rasterized design layoutportion to compute the overall parasitic effect on (e.g., the overallparasitic capacitances experienced by) each route in the supplied designlayout. Instead of directly outputting an overall parasitic value foreach route, the MTN in other embodiments generates parasitic parametersfor each route, and the process in these embodiments computes theoverall parasitic value(s) for each route by using another solverprocess.

At 2015, the process 2000 discards any identified route that hasunacceptable parasitics (e.g., an overall parasitic capacitance valuethat exceeds a threshold capacitance value). When performing the process2000 during a rip-up-and-reroute operation, the operation 2015 can ripout (i.e., discard) more than one route when more than one route haspoor parasitics. At 2020, the process then uses one or more conventionalrouting processes to identify a new route for any net that had its routediscarded at 2015, if any such route was discarded at 2015. In someembodiments, the process 2000 performs the operations 2015 and 2020 onthe design layout that contains the set of routes identified at 2005 andthat is defined in the contour domain. After ensuring that theparasitics for any newly defined route is acceptable, the process 2000then ends.

As processes has evolved, open-via defects have become one of the mostimportant failure mechanisms. Vias fail due to random defects, cutmisalignment, thermal stress-induced voiding effects, orelectromigration. In some embodiments, routers that are aware of theseeffects and take steps to mitigate them, provide more reliable solutionsthan those that are not. Redundant via-insertion is one existingtechnique used to improve reliability and yield. A failing via that hasa fault-tolerant, redundant via partner need not be an issue.

FIG. 21 illustrates an example of a double-pair redundant via insertion.In this approach, each via is accompanied by a redundant via partner.Each via is shown with a black square center, while its correspondingredundant via is shown with a gray square center. Double-pair vias havebeen found to lead to failure rates which are 10-100 times smaller thansingle vias. In some of todays via insertion processes, vias arecategorized as alive, dead and critical vias. FIG. 22 illustratesexamples of dead, critical and alive vias. Alive vias have at least one,and possibly more redundant via possibilities. Alive vias within only asingle redundant via possibility are termed critical vias, and vias thathave no redundant via partners are termed dead vias.

In some embodiments, redundant via insertion are performed as a postprocessing step after routing is complete. However, if the router insome embodiments minimizes the number of dead vias (via locations forwhich no redundancy possible) or critical vias (via locations for whichonly a single redundancy is possible), the post-layout via insertionrate is significantly improved.

FIG. 23 illustrates an example of a process for redundant-via-awaredetailed routing in four stages 2352-2358. As shown, in first stage 2352illustrated in image (a), a net is shown that needs to be routed fromthe source pin S 2302 to the target pin T 2304. The second stage 2354illustrated in image (b) shows the potential locations for insertingredundant vias before the routing operation is performed. Threeredundant vias 2322, 2324, and 2326 are defined for pre-existing route2320, while four redundant vias 2332, 2334, 2336 and 2338 are definedfor pre-existing route 2330. Each redundant via location is assigned aredundant via cost. The via cost for each via is the cost assigned to anew route being placed in such a way as to block that via. Per thisencoding, some redundant vias have lower costs than others, as there aremore possibilities for alternates.

The third stage 2356 illustrated in image (c) shows the routerconsidering two possible routes for the net under consideration. Onerouting path 2306 goes to the left and then up, while the other routingpath 2308 goes up and then to the left. The routing path 2306 crosses(or eliminates the possibilities) for vias in a higher cost manner thanthe second routing path 2308. The first path incurs a via cost of ⅚(which is the sum of the individual via costs eliminated by this routecandidate), while the second path incurs a cost of just ¼. Hence, thefourth stage 2358 illustrated in image (d) shows that theredundant-via-aware router has defined a route 2340 for the net with thesource S and target T pins, by selecting and completing the latterrouting path 2308.

Some embodiments use a neural network to rapidly compute the lowest-costpath, replacing the prior art steps of first computing all the redundantvia locations and then enumerating all the possible paths/viaintersections to find the via-cost for each path. Such a network istrained in some embodiments first to make such inferences. To train sucha neural network, some embodiments supply the network with inputs thatcorrespond to images like the first stage 2352 image (a) of FIG. 23 ,and known outputs associated with these input images, with such outputscorresponding to the result from which the neural network is beingtrained (e.g., redundant via location and/or via elimination, etc.).

Hence, given an image like input image (a) of FIG. 23 , the trainedneural network in some embodiments identifies the via insertion solutionillustrated in image (d) of FIG. 23 as the preferred solution. This viainsertion solution has the three redundant vias 2322, 2324, and 2326 forthe pre-existing route 2320, and the three redundant vias 2332, 2334 and2336 for the pre-existing route 2330. In some embodiments, the trainedneural network also produces the route 2340 illustrated in the image(d). In other embodiments, the trained neural network just produces thevia insertion locations for the router to use to modify the pre-existingroutes 2320 and 2330, and then leaves it to this router to subsequentlyidentify in a subsequent routing operation the route for the net withthe source S and target T pins.

Not all via costs are equal. Some redundant via locations are ‘better’than others due to the effects of lithography and manufacturing processvariations, even in the face of advanced OPC. If two paths are deemedequal-cost by the process described above, either could be selected bythe router. To identify the better solutions due to lithographic andmanufacturing issues, some embodiments use a digital twin MTN todetermine more accurate via costs. For example, in some embodiments, afront-to-back digital twin is used to precisely predict the manufacturedcontours for the various candidate redundant via locations.

Vias will be manufactured as ‘circles’ (approximately), which will varyin uniformity and area. The digital twin MTN of some embodimentsproduces predicted shapes of vias in view of lithography andmanufacturing process variations. From these shapes, the router in someembodiments then selects the new routing candidate path that results inthe largest area/most uniform vias for the previously routed paths, allother things being equal.

In other embodiments, during a post-processing operation prior to theinsertion of the redundant vias, a trained neural network is used torapidly identify the areas of the routed design most in need ofredundant via insertion. This introduces a new concept ofmissing-redundant-via hotspots in a design. In some embodiments, an areaof the design so-identified is targeted for an additional round ofrouting refinement, e.g., rip-up and reroute operations, and the routercalled again. A trained-neural network approach in some embodiments issubstantially faster than iterating over the net shapes in detail tocompute this information, while still offering a sufficiently accurateresult.

FIG. 24 illustrates a process 2400 that some embodiments use to identifycandidate redundant via insertion locations. This process uses an MTN toidentify these candidate locations for inserting vias into the designlayout. As shown, this process starts by a router defining (at 2405) oneor more routes for one or more nets in a portion of the IC designlayout. At least one of these defined routes is a multi-layer route thattraverses multiple interconnect layers to connect at least two pins of anet. In some embodiments, a router uses the process 2400 for each routethat it defines for each net, while in other embodiments, the routeruses the process 2400 for a group of routes that it defines for a groupof nets (e.g., as part of a rip-up-and-reroute operation). To defineeach route, the process 2400 uses (at 2405) one of the traditionaldetailed routing processes that are commonly used today to definedetailed routes.

At 2410, a rasterized (i.e., pixelated) version of the design layoutportion is supplied to the MTN. When the router defines its routes inthe contour domain, a rasterization operation has to be performed totransform the contour/geometric definition of the design layout into thepixel-domain in which the shapes in the design layout are represented byactual pixel values, e.g., such as those described above.

Next, at 2415, the MTN processes the rasterized design layout portion toidentify locations for inserting redundant vias in the design layout.FIG. 25 illustrates an example of this operation. This figureillustrates an MTN 2500 processing a rasterized version 2505 of thefirst-stage design layout of FIG. 23 , to identify the via insertionsolution has the three redundant vias 2322, 2324, and 2326 for thepre-existing route 2320, and the three redundant vias 2332, 2334, and2336 for the pre-existing route 2330.

The MTN 2500 outputs these via insertion locations differently indifferent embodiments. In some embodiments, it outputs these locationsin terms of the coordinates of the candidate via locations that the MTNidentifies. In other embodiments, the MTN outputs a pixel-domainrepresentation of the image with the identified candidate via insertionlocations. In still other embodiments, the MTN identifies the vialocations in other ways, e.g., by identifying a route that needs to haveits vias examined.

The MTN 2500 identifies the candidate via locations, as it was placedthrough a training process that supplied lots of known input designlayout portions, and the corresponding output candidate via locations(for each input sample) that were identified by traditionalvia-insertion processes, as further described below. In someembodiments, the MTN 2500 not only identifies candidate via locationsfor insertion into the design layout, but also identifies via locationsthat the router defined for its routes that are candidates for moving orremoval. The MTN in these embodiments can identify the vias to move orremove as the known input/output samples that were used to train the MTNallow the MTN to identify router-defined via locations that are notoptimal (e.g., that create too much congestion or have poormanufacturing or lithographic properties).

The via modification MTN 2500 in some embodiments performs its viamodification operations (e.g., provides its via insertion and/or removalrecommendations) based on the predicted manufactured shapes of the inputIC design layout that it receives. As shown in FIG. 26 , someembodiments first have another MTN 2600 process a rasterized image 2605of a rectilinear design layout to produce another rasterized image 2610of a curvilinear design layout that represents the predictedmanufactured IC associated with the input design layout. Examples ofsuch MTNs are described in the above-incorporated U.S. Pat. Publication20220128899, U.S. Pat. Application 17/992,870, U.S. Pat. Application18/097,272, and U.S. Pat. Application 17/992,897.

In these embodiments, the rasterized image 2610 of the curvilineardesign is then supplied to the via modification MTN 2600, which thenprocesses this curvilinear image to produce its via insertion and/orremoval recommendations. In other embodiments, the via modification MTN2500 is trained to implicitly perform the task of the MTN 2600 in orderto provide, for a given input rectilinear design that it receives, itsvia modification recommendations based on the predicted manufacturedcurvilinear design. In still other embodiments, the via modification MTN2500 receives from the router the predicted manufactured curvilineardesign as the router produces such designs natively.

After the via modification MTN identifies (at 2415) the via locationsthat have to be added or removed from the supplied design layout, theprocess 2400 modifies (at 2420) one or more routes to account for thevia modification(s) specified by the via modification MTN. In someembodiments, the process 2400 performs the operation 2420 back in thecontour domain. Some embodiments use (at 2420) a known via-modificationprocess to add redundant vias at locations identified by the MTN. Insome embodiments, the router implements the via-modification process.For the via modification, the route modification (at 2420) in someembodiments involves modifying the defined routes to include theadditional redundant vias. This modification includes adding theidentified vias to the previously defined routes.

When such an added via requires a previously defined route to beextended on one or more layers traversed by the route, the routemodification includes the necessary extension of the routes. Forinstance, two of the redundant vias 2105 and 2110 in FIG. 21 would notrequire extensions of the previously defined routes as they are definedin the path traversed by these routes, while a third redundant via 2115in this example requires the route 2120 to be extended on both metallayers (i.e., to the x- and y-axis locations of the new redundant via)as it is defined outside of a corner made by this route. Also, in somecases, the pre-existing via 2125 that is defined at this corner mightget flagged by the via modification MTN 2500 as a via that would have tobe removed, e.g., as it might have issues once it is manufactured forbeing too close to a nearby wire or other obstacle. In such a case, therouter would replace the via 2125 with the via 2115.

As mentioned above, the router that called the via modification MTN tocheck its route(s) is the EDA tool that performs the via and/or routemodification operation 2420 in some embodiments. In other embodiments,it is another post-processing EDA tool that performs these operations.In still other embodiments, the via and/or route modification operation2420 is performed by another MTN. In yet other embodiments, one viamodification MTN both identifies the locations of the vias to add and/orremove, and performs the route and/or via modification operations thatare needed to add and/or remove the vias.

Such a via modification MTN is trained to receive rasterized images ofdesign layout portions and to produce rasterized images of modifieddesign layout portions with added vias and/or removed vias, and whennecessary, route modifications to effectuate the desired viamodifications. To train such an MTN, some embodiments use knowninput/output design pairs, with the input designs having one or moreroutes, vias and neighboring structures, and the output designs thatcorrespond to these input designs and that are generated by (i) usingexisting via modification processes followed by (ii) using existingroute modification processes that use the information provided by thevia modification processes.

Conjunctively with the insertion of the redundant vias, the MTN (at2415) in some embodiments can identify vias to remove or to move. Tomove a via, some embodiments discard a first via that is defined along afirst route at a first location and insert a second via along the firstroute at a second location. This movement of the via can be viewed assimply replacing the old via with a new via, or the movement of the oldvia to a new location (assuming that the same identifier is used for thevia at the new or old locations). The movement of the via along a routecan include modification of the route to extend to a new location of thevia on one or more interconnect layers.

The MTN in some embodiments removes or moves the via instead of simplyidentifying the via to remove or move. In these embodiments, the MTN istrained in a training process that uses a first set of known inputdesign layouts with a first set of corresponding known output designlayouts that have (1) a new location for each of one or more vias intheir corresponding input design layouts and (2) possibly one or moreroute modifications that modify one or more routes to traverse to a newvia location. The known input design layouts are individually fedthrough the MTN during training to produce a generated output designlayout that is part of a second set of generated output design layouts.Each generated output design layout includes (1) a new location for eachof one or more vias in its corresponding input design layout and (2)possibly one or more route modifications that modify one or more routesto traverse to a new via location. For each training batch, thedifferences between the first and second sets of output design layoutsare used to generate a loss function value, which is used to adjust aset of trainable parameters of the MTN. Multiple training batches arefed through the MTN, to fully train the adjustable set of trainableparameters of the MTN.

Instead of identifying candidate via locations to add, move or remove,the MTN of the process 2400 in other embodiments simply identifies (at2415) via locations that should be re-assessed by a traditionalvia-modification and/or route-modification operation. These identifiedvia locations are called via “hotspots” in some embodiments. They arevia locations in routes defined by a router that need to be re-assessedby the router or a via-modification process used by the router in orderto move the via location and/or to add additional redundant vias aboutthis location in order to alleviate the hotspot problem identified bythe process 2400. To train these hotspots, the MTN in some embodimentsreceives multiple pairs of known inputs/outputs, with each input beingan extracted portion of a design layout and the input’s correspondingoutput being one or more via hotspots that an existing via analysisprocess identified as potential problem locations for placing vias orfor needing additional redundant vias.

FIG. 27 illustrates a process 2700 of some embodiments that uses adigital twin MTN to just identify via hotspots, and then uses anotherprocess to analyze the identified hotspots in order to add redundantvias, move vias or remove vias. The first two operations 2405 and 2410of this process are similar to the operations 2405 and 2410 of process2400 of FIG. 24 . However, unlike the MTN used by process 2400, the MTNused by process 2700 identifies (at 2715) locations in the input designlayout that need to be further analyzed for via modification operations(i.e., identifies via hotspots in the input design layout).

This output is expressed differently in different embodiments. In someembodiments, it is expressed with “hotspot” tags being associated withthe routes and/or via locations that need further analysis in the inputdesign layout. In other embodiments, this output is identified bygeometric markers that are entered in the design layout (e.g., by one ormore circular regions in the design layout) to identifyroute-crossing-locations and/or via-locations that need to be furtherexamined by a via-modification operation. Still other embodiments useother techniques to identify the via locations that need to be furtheranalyzed by a via-modification process.

Like the MTN used by the process 2400 in some embodiments, the MTN usedby the process 2500 performs its via hotspot detection based on thepredicted manufactured shapes of the input IC design layout that itreceives. This MTN accounts for the predicted manufactured shapes in thesame way as the MTN used by the process 2400 in some embodiments.

At 2720, the process 2700 identifies and removes any route that needs tobe ripped out of the input design layout in order to address thedetected via hotspot problem (e.g., to improve the performance of thevias at the identified hotspot locations). A route can get ripped out at2720 for a variety of reasons, such as (1) the route creating congestionat a via location, (2) the route being too close to a desired vialocation (e.g., once the predicted manufactured shapes are taken intoaccount) of another route, and (3) the route having one or more viaswith poor characteristics (e.g., size, location, performance, etc.),etc.

For any net that had its route ripped out at 2720, the process thendefines (at 2725) a new route. In some embodiments, this entails addingthe net to the list of unrouted nets and then performing the routingoperation one more time for this net to identify a route for it. In someembodiments, the router defines one or more new constraints (e.g.,location constraints, via location constraints, or other viaconstraints) for the router to use while trying to identify a new routefor this net. In some embodiments, the process 2700 performs theoperations 2720 and 2725 on the design layout defined in the contourdomain. After 2725, the process ends.

FIG. 28 illustrates a process 2800 for training a neural network toperform the operations of the via modification MTN 2500 of someembodiments. As shown, the process initially identifies (at 2805)several input IC design layout samples, e.g., by extracting thesesamples from a previously defined IC design. Each of these samples isselected to have at least one multi-layer route with at least one via,although typically each sample has more than one via for one or moreroutes. Each input sample in some embodiments includes multiple imagesof multiple layers of wiring and interconnects. Also, each input samplecan include pins, routes, vias and obstacles about which the routes andvias have to be defined.

Next, at 2810, the process 2800 feeds each input design layout samplethrough an MTN that predicts the shapes of the components in the inputsample at a subsequent manufacturing stage (e.g., at a wafer simulationstage or at the manufactured IC stage). The process 2800 does thisoperation in order to train its via modification MTN to account for thepredicted manufactured shapes of the design layout components. In otherembodiments, the process 2800 uses other techniques (e.g., wafersimulation) to produce the known output shape of the components in theinput sample at a subsequent manufacturing stage. For instance, in someembodiments, the process extracts the inputs and outputs from thedatabase of prior design/manufacturing operations, where the inputsamples are from the prior produced physical design layouts and theoutput samples are from the outputs of the prior wafer simulationprocesses.

The manufactured shapes produced at 2810 serve as the known inputsamples that are used to train the via modification MTN. After 2810, theprocess 2800 then generates (at 2815) the known output for each inputsample produced at 2810. In some embodiments, the process 2800 uses amodified version of a currently used via-modification process togenerate the known output for each known input. One suchvia-modification process is described in “Post-Routing Redundant ViaInsertion for Yield/Reliability Improvement,” by Lee and Wang, inProceedings of the 2006 Asia and South Pacific Design AutomationConference (ASP-DAC ‘06), January 2006, pgs. 303-308.

In some embodiments, the process identifies the intersection of thepredicted manufactured curvilinear shapes that form the via on two ormore layers in order to determine the predicted overlap shape of thevia, and then uses this predicted overlap shape to determine whether tokeep this via, discard the via or require additional redundant via(s)for this via. To compute the predicted via overlap shape based on thepredicted manufactured curvilinear shapes of the via, some embodimentsuse the processes described in the above-incorporated U.S. Pat.Application 17/992,897. In some of these embodiments, the processdiscards a particular via if its predicted overlap shape is smaller thana first threshold, and requires additional redundant vias to be definedfor the particular via when its predicted manufactured overlap shape islarger than the first threshold but smaller than a second threshold. Insome of these embodiments, the predicted overlap shape for theparticular via accounts for structures that neighbor this via ondifferent layers.

The via modification process in some embodiments analyzes an inputdesign layout sample to identify locations (1) to place redundant viasand/or (2) to move or remove vias defined by the router from the routesdefined by the router. In some embodiments, the via modification processis also a route modification process that also modifies the routes inthe input design layout to actually insert redundant vias, movepreviously defined vias and/or remove previously defined vias.

Next, at 2820, the process 2800 uses the input samples generated at 2810and their corresponding output samples generated at 2815, to train thevia modification MTN. To train the neural network, some embodiments feedeach known input sample through the neural network to generate anoutput, and then compare this generated output to the known output ofthe input to identify a set of one or more error values. The errorvalues for a group of known inputs/outputs are then used to compute aloss function, which is then back propagated (at 2825) through theneural network to train the configurable parameters (e.g., the weightvalues) of the neural network. In some embodiments, the MTN receives (at2820) each input sample defined in the pixel domain.

At 2830, the process determines whether it has sufficiently trained thevia modification MTN. If not, the process returns to 2805 to continueits training operations. Otherwise, the process ends. Once trained byprocessing a large number of known inputs/outputs, the neural networkcan then be used to facilitate routing operations of some embodiments by(1) identifying locations for adding vias, removing vias, or movingvias, (2) modifying routes to perform any of these via modificationoperations, or (3) simply identifying via hotspot locations in thedesign layouts.

Instead of identifying candidate via locations to add, move or remove,the training process 2800 in some embodiments trains the MTN to simplyidentify via locations that should be re-assessed by another traditionalvia-modification and/or route-modification operation. These “hotspot”locations need to be re-assessed by a router or a via-modificationprocess used by the router in order to move the via location and/or toadd additional redundant vias about this location in order to alleviatethe identified hotspot problem.

In these embodiments, the MTN is trained in a training process that usesa first set of known input design layouts with a first set ofcorresponding known hotspot outputs that identify via hotspot locationsin the input design layout. The known input design layouts areindividually fed through the MTN during training to generate a secondset of predicted via hotspot output location in the input designlayouts. For each training batch, the differences between the first andsecond sets of via hotspot output locations are used to generate a lossfunction value, which is used to adjust a set of trainable parameters ofthe MTN. Multiple training batches are fed through the MTN, to fullytrain the adjustable set of trainable parameters of the MTN. Duringtraining, the input and output samples of the MTN are images ofmulti-layer designs as described above.

FIG. 29 illustrates a process 2900 of some embodiments that uses adigital twin MTN to generate the predicted manufactured shapes of vias,and then analyzes these shapes to determine whether it needs to insertadditional redundant vias and/or to move any vias. As shown, thisprocess starts by a router defining (at 2905) one or more routes for oneor more nets in a portion of the IC design layout. At least one of thesedefined routes is a multi-layer route that traverses multipleinterconnect layers to connect at least two pins of a net. In someembodiments, a router uses the process 2900 for each route that itdefines for each net, while in other embodiments, the router uses theprocess 2900 for a group of routes that it defines for a group of nets(e.g., as part of a rip-up-and-reroute operation). To define each route,the process 2900 uses (at 2905) one of the traditional detailed routingprocesses that are commonly used today to define detailed routes.

At 2910, a rasterized (i.e., pixelated) version of the design layoutportion is supplied to the MTN. When the router defines its routes inthe contour domain, a rasterization operation has to be performed totransform the contour/geometric definition of the design layout into thepixel-domain in which the shapes in the design layout are represented byactual pixel values, e.g., such as those described above.

Next, at 2915, the MTN outputs a rasterized design layout portion thatincludes the predicted manufactured shapes for the components (e.g.,routes, via contacts, etc.) in the design layout portion that the MTNreceived as input. In some embodiments, each predicted manufacturedshape is drawn by three curvilinear contours representing threevariations of a manufacturing parameter. The training and use of such anMTN is further described in the above-incorporated U.S. PatentApplications.

At 2920, the process 2900 performs a modified version of a currentlyavailable via-modification operation on the curvilinear output of theMTN. In some embodiments, the process 2900 performs the operation 2920and subsequent operation 2925 on the design layout defined in thecontour domain. Before performing this operation, the MTN output istransformed from the pixel domain to contour domain as thevia-modification operation is performed in the contour domain. Thisvia-modification operation in some embodiments analyzes the curvilinearMTN output to determine whether additional redundant vias need to bedefined, or whether any vias need to be moved in or removed from theinput IC design layout portion.

In some embodiments, the via-modification operation identifies theintersection of the predicted manufactured curvilinear shapes that formeach via on two or more layers in order to determine the predictedoverlap shape of the via, and then uses this predicted overlap shape todetermine whether to keep this via, discard the via or requireadditional redundant via(s) for this via. To compute the predicted viaoverlap shape based on the predicted manufactured curvilinear shapes ofthe via, some embodiments use the processes described inabove-incorporated U.S. Pat. Application 17/992,897. In some of theseembodiments, the process discards a particular via if its predictedoverlap shape is smaller than a first threshold, and requires additionalredundant vias to be defined for the particular via when its predictedmanufactured overlap shape is larger than the first threshold butsmaller than a second threshold. In some of these embodiments, thepredicted overlap shape for the particular via accounts for structuresthat neighbor this via on different layers.

Instead of using a traditional via-modification operation, someembodiments use (at 2920) another via-modification MTN to analyze thecurvilinear MTN output to determine whether additional redundant viasneed to be defined, or whether any vias need to be moved in or removedfrom the input IC design layout portion. In these embodiments, therasterized curvilinear MTN output is then supplied to the viamodification MTN, which then processes this curvilinear image to produceits via insertion and/or removal recommendations.

At 2920, the process 2900 identifies and removes any route that needs tobe ripped out of the input design layout in order to address a detectedvia problem that cannot be solved by adding redundant vias or movingvias. A route can also get ripped out at 2920 for a variety of otherreasons, such as (1) the route creating congestion at a via location,(2) the route being too close to a desired via location (e.g., once thepredicted manufactured shapes are taken into account) of another route,and (3) the route having one or more vias with poor characteristics(e.g., size, location, performance, etc.), etc.

Lastly, at 2925, the process 2900 (e.g., the via-modification operation)modifies any route for which the operation added redundant vias or movedvias. For any net that had its route ripped out at 2920, the process2900 also defines (at 2925) a new route. In some embodiments, thisentails adding the net to the list of unrouted nets and then performingthe routing operation one more time for this net to identify a route forit. In some embodiments, the router defines one or more new constraints(e.g., location constraints, via location constraints, or other viaconstraints) for the router to use while trying to identify a new routefor this net. After 2925, the process ends.

Edge-based OPC is a photolithography enhancement technique commonly usedto compensate for image errors due to diffraction or process effects.OPC comes into play in the making of semiconductor devices and accountsfor the limitations of light to maintain the edge placement integrity ofthe original design, after processing, into the etched image on thesilicon wafer. These projected images appear with irregularities such asline widths that are narrower or wider than designed, and are amenableto compensation by changing the pattern on the photomask used forimaging. Other distortions (such as rounded corners) are driven by theresolution of the optical imaging tool and are harder to address. Suchdistortions, if not addressed, significantly alter the electricalproperties of what is being fabricated. Optical proximity correctioncorrects these errors by moving edges or adding extra polygons to thepattern written on the photomask.

As process geometries have decreased, routing has faced the need toreconcile a growing interdependency between lithography and layoutdesign. Printability and reliability of manufacturing have now becomekey concerns. Modern routers need to be aware of the limitations ofmanufacturing and aware of key advanced manufacturing-related flow stepssuch as OPC (optical proximity correction), variation in Edge PlacementErrors (EPE), etc. The former problem requires that routers become awareof their impacts on the downstream OPC flow, and attempt to create moreOPC-friendly routing solutions. The latter requires that routers go onestep further and become aware not only of the OPC process itself but infact, also of final manufacturing and the final edge placements inmanufactured interconnects.

Some have suggested an OPC-friendly routing is an OPC-aware multilevel,full-chip gridless detailed router. The overall technique uses amulti-level approach to routing as described above. This routerintegrates global routing, detailed routing, and congestion estimationat each level of multilevel routing. In addition, the router in someembodiments reduces OPC-pattern-feature requirements, making the job ofthe downstream OPC tool easier. As the router seeks to optimize (e.g.,minimize) path length (i.e., wirelength) using a shortest path process(such as Dijkstra’s), it incorporates an additional cost, which is theOPC cost. The router therefore seeks to both minimize path length andoptimize for OPC friendliness at the same time, with the latter achievedby introducing a rule-based OPC approach into the multilevel-routingframework, on the basis that a model-based approach is tootime-consuming. However, rule-based approaches are not as accurate asmodel based approaches, and as process geometries have shrunk evenfurther, OPC requirements are significantly higher than as modeled.

Today’s modern nanometer geometry processes require a very complex formof OPC which includes SRAF (sub-resolution assist features) insertion oreven full ILT (Inverse Lithography Technology). Some embodiments replacethe simple rule-based OPC method and its associated cost functioncalculation with one based on a full front-to-back digital twin MTN.Some embodiments also replace the OPC cost during wirelengthoptimization with a very different type of cost, a cost associated withthe final manufactured interconnect contours, which takes OPC methods(including advanced OPC methods such as ILT) into account, along withmanufacturing itself.

In the prior approach, an OPC cost along with a wirelength cost isincluded when performing wirelength optimization. The OPC cost itselfhas two components, the first of which is an ‘actual’ OPC costassociated with nets that have already been routed, and the second ofwhich is an ‘estimated’ OPC cost associated with the routes that remainto be routed. In the former case, the actual cost of a line is based onthe OPC effect caused by the neighboring, already routed lines. In thislatter case, the estimated OPC cost is taken as a worst case estimation,by assuming that a line segment will be fully surrounded by adjacentlines when routing is complete. The rule-based approach assumes that theOPC cost for a line is proportional to its length and width, byconsidering the likely placement of OPC features such as hammerheads atthe line ends, and bias features on long line edges.

Some embodiments use a trained OPC-process digital twin to predict theactual OPC features that will be inserted for a given routing solution.These embodiments move from a simple rule-based approach to somethingthat is more OPC-model-based. In this case however, rather than being aphysics-based model, the model now is a trained convolutional neuralnetwork, i.e., a network which has been trained to produce edge-basedOPC features such as line biases, hammerheads and the like as shown inFIG. 5 that was described above.

This model runs with a rasterized image representing the route candidatesolution and immediate neighborhoods as input, and produces a rasterimage representing what the OPC tool would produce in terms of featuresas output. In some embodiments, the OPC digital twin is trained toproduce curvilinear OPC features and SRAFs, such as those that would beproduced by an ILT-based OPC tool. In some embodiments, a cost functionis encoded that is based on a measurement of difference between theinput image and the output image. The more ‘different’ the output(OPC-corrected) image is from the input (route-candidate image), thehigher is the OPC cost associated with the route. This difference insome embodiments expresses the degree of difficulty in performing asubsequent OPC operations after physical design (e.g., after therouting). Hence, by selecting routing solutions with lower expected OPCcosts, the router can ensure that the subsequent OPC operation will beeasier.

FIG. 30 illustrates examples of mask patterns without OPC and withedge-based OPC. The top half of this image shows the printed patterns3005 that result from a non-OPC enhanced T-shaped pattern 3010 on themask, while the bottom half of this image shows the printed patterns3015 that result from the OPC-enhanced T-shaped pattern 3020 on themask. The ‘difference’ between the two images representing thenon-OPC-enhanced pattern 3010 and the OPC-enhanced pattern 3020 isencoded into the OPC cost function in some embodiments. The figure alsoillustrates improvement in the printability of the patterns bypresenting on its right-side the degraded printed pattern 3005 that isproduced from the non-OPC-enhanced pattern 3010 near the more T-shapedprinted pattern 3015 that is produced from the OPC-enhanced pattern3020.

In some embodiments, the output cost is determined by a post-processingoperation given the pre- and post-OPC images (as produced by, forexample, a fully convolutional neural network) as input. In someembodiments, the difference function is based on image processingdifference operations, such as cross correlation, structural similarity,peak signal to noise ratio and the like, or other pixel-based differencefunctions are employed (such as intersection over union IOU, i.e., theJacquard Index). Under this approach, the fully convolutional neuralnetwork is trained with image pairs with the input images being pre-OPCroute candidate images, and the output images being post-OPC-correctedimages, obtained by rasterizing the outputs of an OPC tool. A postprocessing operation then computes the OPC cost by analyzing the outputOPC-corrected images. The router in some embodiments then uses thispost-processing computed OPC cost in its routing optimization process,e.g., along with wirelength minimization and/or congestion reductionprocesses.

In other embodiments, the OPC cost is directly predicted by the neuralnetwork, for example by use of a standard convolutional neural networkwith a convolutional base and followed by a dense or fully connectedoutput with a linear final activation function, acting as a regressor.Under this approach, the convolutional neural network is trained with(X,Y) data pairs where the inputs X are pre-OPC route candidate images,and the outputs Y are scalar values representing an OPC cost. The groundtruth Y OPC cost values used to train the model are obtained by runningan OPC tool and computing the cost, e.g., via some kind of differencefunction when producing the training data. During inference, the routerin some embodiments uses the OPC cost output from the digital twin MTNin its routing optimization process (e.g., along with wirelengthminimization and/or congestion reduction processes). By including costfunction components related to a more accurate model-based OPC, therouter is guided to produce a more OPC-friendly routing solution.

FIG. 31 illustrates another example of OPC corrected image. The Γ-likerectilinear shape 3102 (displayed in a first color, e.g., blue) is whata chip designer would like printed on the wafer. The shape afterapplying optical proximity correction 3104 is displayed in a secondcolor (e.g., green) with the jagged edges. The curved contour 3106(displayed in a third color, e.g., red) is how the shape actuallyprints, quite close to the desired Γ-like target. This form of OPC hasbeen successfully applied at small geometry processes, but has not beeneffective for today’s smallest, nanometer scale processes.

During routing, some embodiments use a digital twin MTN to performedge-based OPC to quickly produce digital layout component shapes with‘jagged’ edges (referred to below as ‘jagged’ output images). Given adesired image (Γ-like rectilinear shape 3102) as input, the digital twinMTN produces the OPC-corrected shape 3104 with the jagged edges. In someembodiments, the edge-based OPC digital twin is in the form of a neuralnetwork, such as a fully convolutional network. The network is trainedby exposing it to a large number of X,Y samples, where the X values areimages corresponding to the desired-to-be-manufactured shapes, and the Yvalues are the corresponding ‘jagged’ shapes determined by one of theexisting edge-based OPC tool. The OPC shapes produced by the edge-basedOPC tool will typically include hammerheads, serifs, and line biasfeatures (such as those shown in the above-described FIG. 5 ), whichmodify the edges/corners of the originally drawn layout shapes.

In some embodiments, a post-processing operation is performed on thejagged output images produced by the digital twin MTN that is usedduring routing to produce OPC-corrected jagged edge shapes for assessingthe quality of one or more routes contained in a routing solution forone or more nets. This post-processing operation quantifies an OPC costthat the router can then use to assess or re-assess the routes in itsrouting solution, as mentioned above. One post-processing operation insome embodiments quantifies the complexity level of an OPC-correctedjagged edge shape by counting the number of edges in the shape, with thehigher edge number indicative of a higher OPC complexity score.

In some embodiments, the edge-based OPC solution produced by the digitaltwin does not need to be perfect, because in these embodiments theprimary use of the digital-twin provided solution is in computing an OPCcost to be used during optimization within an OPC-aware detailed router.As long as the digital-twin provided solution is sufficiently accurateto be used to compute an OPC cost, it is acceptable. As previouslymentioned, in some embodiments, the OPC cost is related to thedifference between the pre-OPC and post-OPC images, e.g., a ‘difference’figure computed by signal processing functions such as crosscorrelation, structural similarity, peak signal to noise ratio and thelike, or other pixel-based difference functions are employed (such asintersection over union IOU, i.e., the Jacquard Index). As long as the‘cost’ of the digital-twin produced OPC solution correlates well withthe corresponding cost produced by a detailed, computational OPC tool,it benefits the OPC-aware router.

For bleeding edge processes and advanced IC designs, edge-based OPC isinsufficient for reliably printing interconnect shapes. Modernapproaches to OPC now include ILT (Inverse Lithography Technology),either partially or completely. In order for a router to be OPC-aware ina manner that works for such advanced designs, the OPC digital twinneeds to be ILT-based.

FIG. 32 illustrates an example of an ILT-based OPC output that shows amask before and after ILT. The mask before the ILT has rectilinearshapes 3202, while the mask after ILT has curvilinear shapes 3204. Inthis example, the rectilinear shapes 3202 that are part of an originallydrawn pre-OPC mask are superimposed on the curvilinear masks 3204produced by the ILT tool. This figure also shows several SRAFs 3206,which are sub-resolution assist features that are inserted in the maskto help generate an eventual IC that has curvilinear interconnect linesthat try to match the desired rectilinear shapes 3202 as much aspossible.

Like the edge-based OPC digital twin of some embodiments, the ILT-baseddigital twin of some embodiments is trained via a large number of X,Ysamples. Each X value is a set of one or more mask images correspondingto the desired-to-be-manufactured shapes, while each Y value is a set ofone or more mask images comprising the corresponding ‘curvy’ shapesdetermined by a commercial ILT-based OPC tool, such as TrueMask-ILT.

In other embodiments, each X is the physical design layout shape (e.g.,a design layout after a routing operation), while each Y is a set of oneor more mask layout shapes that would result after an ILT operation. Arouter can use the MTN in these embodiments to produce the ILT-optimizedmasks, which another process during routing can analyze to derive acomplexity score/cost for the ILT-optimized masks for the router to usein its route selection process. Still other embodiments train an MTN totake an input physical design layout during routing and directly outputan ILT-based cost that expresses a cost for the eventual set ofILT-optimized masks. A router can then use the costs produced by such anMTN during routing to perform its route selection (e.g., to selectroutes at least partially based on the predicted ILT-cost).

FIG. 33 illustrates examples of images produced by an ILT-based digitaltwin MTN of some embodiments. Specifically, it shows three curvilinearoutput images of the ILT digital twin MTN of some embodiments on theleft next to three real curvilinear mask patterns generated from anindustry leading ILT tool on the right. As for the edge-based OPC case,in some embodiments a cost value is associated with the ILT processing,or a routing solution’s ‘amenability’ to ILT-based OPC processing, bycomparing the digital-twin produced ILT solution image with the pre-OPCrouting candidate solution image provided by the router.

In some embodiments, signal processing functions such as crosscorrelation, structural similarity, peak signal to noise ratio and thelike, or other pixel-based difference functions (such as intersectionover union IOU, i.e., the Jacquard Index) are employed to compute theILT ‘cost’. The more different the digital-twin-produced ILT image fromthe router-produced candidate solution image, the more ILT-‘unfriendly’it tends to be. As for the edge-based OPC case, thedigital-twin-produced ILT image does not have to be perfect, but closeenough to the corresponding image produced by an ILT tool for the coststo be well correlated.

To train an MTN to directly produce the ILT cost, some embodiments trainan MTN or a traditional ILT processing tool to first generate the set ofILT-optimized mask images for each physical design input layout shape X,then generate the cost of the set of ILT-optimized mask images, and thenuse this cost as the known output Y for the known input X. Usingnumerous such known input/output pairs X, Y, these embodiments train theMTN to directly output an ILT-based cost for each routing solution thatthe router provides the MTN during routing.

FIG. 34 illustrates a process 3400 for training a neural network toperform an OPC operation to produce OPC-adjusted images for a routingsolution in some embodiments. During routing, a router can use thisneural network to produce OPC-adjusted images for which the router oranother process computes a cost that the router can account for in itsroute-selection operation. As shown, the process 3400 initiallyidentifies (at 3405) several input IC design layout samples, e.g., byextracting these samples from a previously defined IC design. Inaddition to including one or more routes, each input sample can includepins, vias and/or obstacles about which the routes and vias have to bedefined. Each input sample in some embodiments includes one or moreimages of one or more layers of wiring and interconnects.

Each input sample serves as the known input sample that is used to trainthe OPC-adjusting MTN. At 3410, the process 3400 then generates theknown output for each input sample. To generate this known output, theprocess 3400 runs (at 3410) the input sample through a traditionalsequence of operations that starts after the routing operation and endswith the OPC mask generation process to produce the corresponding outputsample with the corresponding OPC shapes. To perform these operationsefficiently for a large number of input/output pairs, the process 3400in some embodiments performs these operations for a large input physicaldesign, and then extracts each input sample from the large inputphysical design and identifies the output sample for each extractedinput sample from the resulting OPC output. Like the input samples, theoutput samples generated at 3410 in some embodiments may be single layersamples or multi-layer samples (also called multi-channel outputs).

Next, at 3415, the process 3400 uses the input samples identified at3405 and their corresponding output samples generated at 3410, to trainthe OPC-adjusting MTN. To train the neural network, some embodimentsfeed each known input sample through the neural network to generate anoutput, and then compare this generated output to the known output ofthe input to identify a set of one or more error values. The errorvalues for a group of known inputs/outputs are then used to compute aloss function, which is then back propagated (at 3420) through theneural network to train the configurable parameters (e.g., the weightvalues) of the neural network. In some embodiments, the MTN receives (at3415) each input sample defined in the pixel domain.

At 3425, the process determines whether it has sufficiently trained theOPC-adjusting MTN. If not, the process returns to 3405 to continue itstraining operations. Otherwise, the process ends. Once trained byprocessing a large number of known inputs/outputs, the neural networkcan then be used to facilitate routing operations of some embodiments byproducing OPC-adjusted images for a given routing solution identified bya router, so that the router or another process can cost this solutionand then use the cost in its route-selection operation (e.g., use thiscost as part of its costing function that it optimizes for finding anoptimal routing solution).

As mentioned above, some embodiments train an MTN to directly output anOPC cost for a routing solution. FIG. 35 illustrates a process 3500 fortraining an MTN in such a manner. This process is similar to the process3400 of FIG. 34 , except that it has the additional operation 3505,which produces a cost for each OPC adjusted output that it produces at3410 for each known input physical design sample, and uses this cost asthe known output for the known input physical design sample during theloss function generation operation 3415. By using a large number of suchknown inputs/outputs (i.e., known physical design layout input portionsalong with the known OPC cost of these input portions) to train a neuralnetwork, the neural network can then be used to facilitate routingoperations of some embodiments by producing an estimated OPC-cost for agiven routing solution identified by a router, so that the router canthen use this cost in its route-selection operation (e.g., use this costas part of its costing function that it optimizes for finding an optimalrouting solution).

FIG. 36 illustrates a process 3600 that a router uses during routing insome embodiments to account for OPC costs in its route selectionoperation. The process 3600 uses a digital twin MTN to perform a quickOPC operation to produce OPC-adjusted component shapes, e.g., shapeswith ‘jagged’ edges. In some embodiments, a router uses the process 3600for each route that it defines for each net, while in other embodiments,the router uses the process 3600 for a group of routes that it definesfor a group of nets (e.g., as part of a rip-up-and-reroute operation).

As shown, this process starts by a router defining (at 3605) one or moreroutes for one or more nets in a portion of the IC design layout. Todefine each route, the process 3600 uses (at 3605) one of thetraditional detailed routing processes that are commonly used today todefine detailed routes. When the routes are multi-layer routes, theroutes include vias. The design layout portion that includes the definedroutes also includes in some embodiments pins connected by the routesand/or obstacles about which the routes and vias have to be defined.

At 3610, a rasterized (i.e., pixelated) version of the design layoutportion is supplied to the MTN. When the router defines its routes inthe contour domain, a rasterization operation has to be performed totransform the contour/geometric definition of the design layout into thepixel-domain in which the shapes in the design layout are represented byactual pixel values, e.g., such as those described above. Eachrasterized solution in some embodiments includes one or more images ofone or more layers of interconnects and vias.

Next, at 3615, the MTN processes the rasterized design layout portion toproduce an OPC-adjusted image that represents a predicted output of theOPC stage for the input routing solution. The OPC shapes produced by theOPC-adjusting MTN can include hammerheads, serifs, and line biasfeatures that modify the edges/corners of the originally drawn layoutshapes, such as those illustrated in FIG. 30 . OPC shapes can alsoinclude edge-based serifs and line-biased modifications, such as thoseillustrated in FIG. 31 . In case of ILT-based OPC, these shapes alsoinclude SRAFs, such as those illustrated in FIG. 32 .

The OPC-adjusting MTN in some embodiments performs its OPC-adjustingoperations based on the predicted manufactured shapes of the input ICdesign layout that it receives. For example, some embodiments first haveanother MTN process a rasterized image of a rectilinear design layoutoutput from a rectilinear router to produce another rasterized image ofa curvilinear design layout that represents the predicted manufacturedIC associated with the input design layout. Examples of such MTNs aredescribed in the above-mentioned and incorporated U.S. PatentApplications.

In these embodiments, the rasterized image of the curvilinear design isthen supplied to the OPC-adjusting MTN, which then processes thiscurvilinear image to produce its OPC-adjusted image. In otherembodiments, the OPC-adjusting MTN is trained to implicitly perform thistask in order to provide, for a given input rectilinear design that itreceives, its OPC-adjusting recommendations based on the predictedmanufactured curvilinear design. In still other embodiments, theOPC-adjusting MTN receives from the router the predicted manufacturedcurvilinear design as the router produces such designs natively, asfurther described below.

After the OPC-adjusting MTN generates (at 3615) the OPC-adjustedimage(s), the process 3600 computes (at 3620) a cost for OPC-adjustedimage(s). In some embodiments, the router that called the OPC-adjustingMTN computes this cost. In other embodiments, the router uses anotheralgorithmic tool or another MTN to compute this cost. The cost that iscomputed by the post-processing operation (at 3620) to represent theOPC-cost of the input routing solution is used (at 3625) by the routerto assess the quality of one or more routes contained in the routingsolution for one or more nets. In other words, this cost quantifies thecomplexity level of the subsequent OPC operation (e.g., the complexityor amount of the features that the OPC operation will have to add), andthe router can use this cost in its route-selection operation (e.g., usethis cost as part of its costing function that it optimizes for findingan optimal routing solution). In some embodiments, the process 3600performs the operations 3620 and 3625 on the design layout defined inthe contour domain. After 3625, the process 3600 ends.

As mentioned above, some embodiments train an MTN to directly output anOPC cost for a routing solution. FIG. 37 illustrates a process 3700 thata router of some embodiments uses to employ such an MTN during routing.The process 3700 is similar to the process 3600 of FIG. 36 , except thatinstead of operations 3615 and 3620 (that use an MTN to produce anOPC-adjusted image and then compute a cost for this image separately),the process 3700 has the operation 3705, which uses the MTN to directlyoutput the cost of the OPC-adjusted image. Process 3700 then uses thiscost in its route selection operation 3625, in the same way as process3600 uses this cost at 3625 of FIG. 36 .

In several of the training or inference examples described above, theinput solution is described as a rectilinear input routing solution.However, some embodiments employ curvilinear routers that producecurvilinear routes. For such cases, some embodiments properly traintheir MTNs to process curvilinear routes accurately. For instance, thetraining of the MTNs in such embodiments uses curvilinear input routingsamples X, with known output samples Y that are computed by other MTNsor by other existing processes (e.g., other wafer simulation processes,via modification processes, OPC processes, ILT processes, etc.) forthese curvilinear input routing samples.

Some embodiments use a multilevel process but instead of computing andleveraging OPC costs in the router cost function (e.g., when performingthe wirelength minimization), a different type of cost function is used.This new cost function in some embodiments again contains twocomponents, one ‘actual’ component associated with already-routed nets,and one ‘estimated’ function associated with yet-to-be-routed nets(e.g., a worst case estimate cost function). However, instead of thecost function being an OPC cost, it is instead taken as a truemanufacturability cost. In some embodiments, raster images are producedfor a routing solution that includes both actually routed segments, andline segments that are fully surrounded by adjacent lines (which takethe place of to-be-routed nets), and used as input to a very differenttrained neural network such as a front-to-back digital twin.

The outputs of the digital twin MTN in some embodiments are thenprocessed to produce an output cost that relates to manufacturability interms of printability and/or reliability. Here, the final output cost insome embodiments represents a curvilinear DRC cost associated with theexpected as-manufactured interconnect associated with the routingsolution.

One simple DRC cost example would be related to the minimum spacebetween two curvilinear manufactured routes. After manufacturing,curvilinear routes with smaller wire spacings below a certain thresholdimply poorer manufacturability and a higher likelihood of bridge faults.A component of the DRC cost in some embodiments is then a measurement ofthe minimum distance between any two such manufactured interconnects.

Another is a cost associated with the minimum width of a manufacturedinterconnect wire in some embodiments. Excessively narrow manufactured(e.g. those associated with excessive pinching) in some embodimentsleads to ‘open’ circuits either directly after manufacturing, orsometime later after electromigration has occurred in the circuit (areliability issue). Hence, the DRC cost in some embodiments is relatedto the minimum width of the manufactured wire segments, taking theirinner manufactured contours into account. Accordingly, some embodimentsfollow the same overall approach as for multilevel full-chip, OPC-awaregridless routing, but instead of being OPC-based, becomes fullymanufacturing based, or even reliability based. By including costfunction components related to a more stringent, overall manufacturingcost, the router is guided to produce a more manufacturable, and/or morereliable routing solution.

Some have proposed an Edge Placement Error (EPE)-aware wire spreadingand rip-up process that is performed in a full-chip, detailed router.The process uses fast lithography simulations to determine the edgeplacement errors (EPE) associated with manufactured interconnect shapes(e.g., shapes resulting post OPC). The EPE information is then used toperform wire spreading within the router. Under this approach, wiresthat are too close together so as to optically interfere with each otherduring manufacturing in a deleterious fashion, are spread further apartby the router. Furthermore, the rip-up and reroute process incorporatedwithin the router is modified to take the EPE information into account.Wires that are again found via the fast lithography simulator tooptically interfere with each other during manufacturing, areconstrained to be further apart via the introduction of EPE-awareblockages.

This approach suffers from some major deficiencies, however. In order toreduce the use of OPC tools, it relies on the concept of alithography-simulation-produced, full-chip EPE map, which attempts topinpoint lithography hotspots (presumably OPC is factored into thisstep). The full-chip EPE map is only produced once. The EPE’s associatedwith lithography hotspots are then factored into the wire-spreading andblockage insertion steps of the detailed router. Only after EPE-relatedchanges are made, are the corresponding hotspots locally re-simulated.The approach will fail for today’s nanometer design processes however,as even very small changes produced by a modern router, for a modernprocess, need to be fully OPC corrected, and lithographic simulationalone is insufficient. Full OPC, and highly computationally expensiveInverse Lithography Simulation (ILT)-based OPC processes need to beemployed for most cases, making the approach intractable within ananometer geometry router.

Instead of using an EPE-aware wire spreading and rip-up process, therouter of some embodiments uses a front-to-back digital twin MTN toperform wire spreading and blockage insertion. Given a routing candidatesolution, the digital twin in some embodiments, deployed on modern GPUor TPU hardware, rapidly produces raster images of the manufacturedinterconnect shapes in the presence of manufacturing variations. This isperformed in some embodiments even within the inner loops of thedetailed router.

Curvilinear DRC checks in some embodiments are then rapidly performed bya curvilinear DRC checking digital twin and used to determine if therouting is viable/correct from a manufacturability standpoint. Wirespreading, and rip-up and reroute decisions are now made with respect tothe output from the digital twins. In some embodiments, blockages areinserted where necessary based on the output from the digital twin(s)(e.g., within those areas where curvilinear DRC errors are found), theoffending nets re-routed around those blockages, and the results againverified using the digital twins. Because the digital twins take OPC/ILTinto account, the resulting route solution in some embodiments issuccessfully manufactured using today’s manufacturing flows.

Newer advances in technology and deep learning bring up even moreopportunities for more novel routing approaches leveraging digitaltwins. FIG. 38 illustrates examples of a front-side power delivery 3802,a front-side power delivery 3804 with buried power rails 3810, and aback-side power delivery 3806. A buried power rail is a power rail foundon the semiconductor substrate instead of on a metal layer. The railitself is constructed to run underneath the active layer wheresemiconductor components (i.e., transistors and diodes) are found.Back-side delivery delivers power through the ‘back-side’ of thesubstrate, via through-silicon vias. Both approaches promise the metalpower rails that are typically used to deliver power (e.g., metal 1,metal 2), resulting in new-found freedom for those metal layers foradvanced routing techniques.

Instead of using the lower metal layers for power routing, someembodiments re-purpose the lower metal rails (e.g., M1/M2, or M3/M4etc.) towards another kind of routing. Topological routing is performedon these layers in which ‘pins’ (device connections) come from below. Insome embodiments, these lower layers of metal are allowed to route inmore than the horizontal/vertical preferred directions. In someembodiments, the routing angles are not limited to Manhattan directions,but also includes routing at 45 degree angles. In some embodiments, therouting angles are further opened up to allow 30, 60 degree angles, andin some further embodiments, the routing directions are opened up evenfurther, allowing for true any-angle routing. Examples of using thelower wiring layers (e.g., metal layers 3 and 4) for non-preferreddirection (NPD) routing is described in U.S. Pat. Application18/110,332, which is incorporated herein by reference.

As described in this application, the router of some embodiments triesto connect as many nets as possible by just routing on one single layer,in order to minimize via count and overall interconnect resistance. Incases of those nets for which single-layer interconnections (say onmetal 1 or 3) are not possible, the router will ‘via-up’ to the nextlayer (e.g., metal 2 or 4), and the process is repeated on the nextlayer, attempting to route as many of the previously un-routed nets aspossible on that layer only, using many degrees of freedom in routingdirections. In some embodiments, additional layers above the first twoare also used. Finally, after performing single-layer NPD routing onsome initial number of lower layers (e.g., M1-M3, or M3-M4 etc.), someembodiments use conventional preferred direction (e.g., Manhattan)routers for the remaining metal layers to define routes for theremaining unrouted nets.

In some embodiments, the new router which attempts to route as many pinconnections as possible on a single, low layer of interconnect, is freeto use multiple degrees of freedom in routing directions, as previouslydescribed. In some embodiments, it routes the nets in a ‘curvy’ orrubber-band like manner to minimize via count, trading off some amountof ‘meandering’ in a net route to avoid the introduction of a via. Theidea is that the additional extra length incurred in such a lengthincreases the resistance and/or capacitance by only a small fractioncompared to that of the via that is avoided. In some embodiments, therouting is via the rubber-band routing technique, coupled with thefront-to-back digital twin. The rubber-band routing technique finds anapproximate solution to the wire route, the results of which are thenfine-tuned by the use of the front-to-back digital twin.

In other embodiments, a router exploits eight compass directions (e.g.,0, 45, 90, 135, 180, 225, 270, 315 degree wiring) or a larger number ofdirections on all layers without the artificial constraint of apreferred direction, providing the benefits of diagonal wiring withoutthe penalty of introducing extra vias. The results of this routing arethen fine-tuned by the use of the front-to-back digital twin. Thedigital twin is used to determine the actual curved manufactured shapesthat correspond to the ‘ideal’ shapes. At this point, in someembodiments, curvilinear design rule checking is run via another digitaltwin and any remaining manufacturability issues identified. In someembodiments, any routes that remain in violation of the curvilineardesign rules are then modified (e.g., by a rip-up and reroute-likeprocess). Should any nets still fail to be routed after this stage, theyare considered for routing on the layer above in some embodiments.

In other embodiments, the routes produced via the process above arefurther refined via an additional novel application of the front-to-backdigital twin. The shapes produced by the process above are not justinspected/predicted by the front-to-back digital twin, but in fact thedigital-twin-produced curvilinear shapes are then further used toreplace (substitute for) one or more of the shapes produced above. Theadvantage is that unlike the original shapes, the curved shapes areknown to be ‘more readily manufacturable’ by construction (since theyhave been determined by the digital twin, and are curvilinear).

Curvilinear designs are inherently more manufacturable than designs with‘sharp corners’. In some embodiments, a final curvilinear design rulechecking is run via yet another digital twin and identifies anymanufacturability issues (e.g., if only some of the routes were‘curvilinear’ in the process above, while others (remaining from therubber band or liquid routers) remain their sharp corners). In someembodiments, any curvilinear routes that remain in violation of thecurvilinear design rules are then further modified (e.g., by a rip-upand reroute-like process followed by more front-to-back digital twinprocessing). Should any nets fail to be cleanly routed after this stage,they are via’d up to the layer above, i.e., deferred to the next layer.The process continues until all available metal layers (assigned to thenew flexible routing paradigm described above) are exhausted, or untilno nets remain to be routed. From that point upwards, in someembodiments, more conventional routing approaches are deployed. In someembodiments, deep reinforcement learning are used in conjunction with,or to replace, the rubber band routing or liquid routing approach.

As mentioned above, graph-based searching techniques are commonly usedto identify global or detailed routes. Popular graph-searchingtechniques include maze processes, line-search processes, and what isknown as the A* search process. FIG. 39 illustrates an example of amaze-routing process that adopts a two-phase approach to a routingproblem. The first approach (3902) is known as filling, and oftenemploys a ‘wave propagation’ technique, in which adjacent grid cells,starting from a ‘source’ cell S (circled in the black-and-whitedrawings), are progressively labelled one by one until a target node T(displayed within triangles) is reached. Once the target T is reached, aretracing step (3904) is then performed to find the shortest path from Tto S, with decreasing labels. If multiple paths are found, the one withthe least amount of detours is often chosen in order to minimize thenumber of bends, or vias. A variety of processes have emerged in termsof the label encoding scheme, the specifics of the search process, andconstraining of the search space, in order to improve performance andmemory use.

Deep reinforcement learning (deep RL) is a subfield of machine learningthat combines reinforcement learning (RL) and deep learning.Reinforcement learning is a process in which an agent learns to makedecisions through trial and error. This problem is often modeledmathematically as a Markov decision process (MDP), where an agent atevery timestep is in a state, s, takes action, a, receives a scalarreward and transitions to the next state, s′, according to environmentdynamics p(s′|s,a). The agent attempts to learn a policy π(a|s) or mapfrom observations to actions, in order to maximize its returns (expectedsum of rewards). In reinforcement learning (as opposed to optimalcontrol) the process only has access to the dynamics p(s′|s,a) throughsampling.

RL considers the problem of a computational agent learning to makedecisions by trial and error. Deep RL incorporates deep learning intothe solution, allowing agents to make decisions from unstructured inputdata without manual engineering of the state space. Deep RL processesare able to take in very large inputs (e.g., every pixel rendered to thescreen in a video game) and decide what actions to perform to optimizean objective (e.g., maximizing the game score). Deep reinforcementlearning has been used for a diverse set of applications including butnot limited to robotics, video games, natural language processing,computer vision, education, transportation, finance and healthcare.

In some embodiments, the action space is set to a set of 6 integervalued actions, representing 4 directional changes (N,S,E,W), and twolayer changes, i.e., via up (U), via down (D). These correspond torouting decisions, where the ‘head’ of the net being routed is advancedin order to maximize the expected long term reward. In some embodiments,a deep-Q network is utilized to solve two-pin routing problems in aserial manner. The deep-Q network in some embodiments is a convolutionalnetwork.

In some embodiments, the state space for using deep reinforcementlearning in the routing area include pixel images representative of therouting problem. In some embodiments, routing is proceeded in a serialmanner. The state space images in some embodiments are multichannelimages, with one set of channels reserved for the position of the pairof pins which are to be routed, and additional channels reserved for thepins for other nets. In some embodiments, additional channels areassigned for each metal layer in the interconnect stack, reflecting thecurrent routing state. To emulate a grid-based routing scenario, thepixels correspond to routing grid locations. A pixel is either occupied(pixel value of 1), or it is not (pixel value of 0).

A routing grid cell in some embodiments is represented by multiplepixels (e.g., 4 pixels, 16 pixels, etc.). In some embodiments, anotherset of image channels (one for each metal layer available) are reservedto show the current position/head of the net being routed. Only one ofthese channels will have a pixel set to 1, indicating the currentrouting position (encoding the current metal layer, and the current(X,Y) location in terms of grid coordinates within that layer).Initially, all metal layer pixels are set to zero (nothing is routed),except for where there are known routing blockages, in which case thecorresponding pixels are set to 1. As the routing/learning proceeds,empty pixels in the state space are ‘filled in’ on the appropriatelayers as the net being routed proceeds from the source pin to thetarget pin. It will be appreciated by those of ordinary skill in the artthat alternative encodings are used in some embodiments.

In some embodiments, the agent is guided to route a net via feedbackfrom a reward function at each step. The reward function is defined as afunction of the action, a, selected by the agent, and the next state,s′. In some embodiments, a large reward value is returned if the nextstate, s′, corresponds to the target pin. In some embodiments, a smallnegative reward is returned otherwise, hence guiding the agent to findthe shortest path from the source to the target pin, in order tominimize the pain accumulated via negative rewards. In some embodiments,additional negative reward components are assigned if nets are routedtoo close to each other for long segments, reflective of the increasedcapacitance and crosstalk between the nets. By incorporating either orboth of front-to-back and capacitance-extraction digital twins into thereward computations for a DRL (deep reinforcement learning) approach todetailed routing, in some embodiments the DRL agent are made extremelycrosstalk-aware and guided to produce finely tuned detailed routingsolutions that minimize crosstalk.

In some embodiments, further large negative reward components areassigned when layer change actions (via up, via down) are chosen. Thesestrongly guide the agent to minimize the via count, and hence overallresistance. In some embodiments, a maximum number of steps are allowed,after which the environment determines that the routing game is ‘done’.The maximum number of steps will relate to the problem size, i.e., theresolution of the routing grid and the size of the routing area.

In other embodiments, the reward function and/or state space images aremade manufacturing-aware. In some embodiments, a front-to-back digitaltwin is employed to take the images corresponding to the ‘ideal’(rectilinear) nets produced by the agent, from which the as-manufacturedcurvilinear images are then predicted. In some embodiments, thecurvilinear ‘as manufactured’ images for each metal layer are includedin the state space images as additional channels. This increases thedimensionality of the state space somewhat, but also allows the agent tolearn to route in a manufacturing-aware fashion by being aware of theimpact that manufacturing has on nets and how neighboring nets affecteach other. In some embodiments, the reward function are furtherenriched in a negative manner to ‘punish’ actions that result inexcessive pinching (inner contours of manufactured nets are two narrow)or excessive bridging likelihood (outer contours of manufactured netsare too close). In some embodiments, the speed with which such ‘asmanufactured’ images are produced is therefore crucial to the operationof the deep reinforcement learning scheme, hence the approach istractable when convolutional neural networks are used to rapidlyinference the manufactured contours.

The above sequential net routing via RL description was with respect toa single-agent, or ‘vanilla’ reinforcement learning approach. In thiscontext, a single agent seeks to accomplish a goal through maximizingtotal rewards. This can still suffer from the net ordering problemsdescribed above. In other embodiments, a multi-agent reinforcementlearning approach is used. Multi-agent reinforcement learning allowsmultiple agents to interact in a common environment. That is, when theseagents interact with the environment and one another, depending on thespecific process, they are observed to collaborate, coordinate, compete,or collectively learn to accomplish a particular task. When applied tothe task of routing, the MARL approach provides a concurrent routingsolution, which is less sensitive to the net ordering problems. In someembodiments, the agents are programmed to act in a purely cooperativemanner, with all agents working toward the same collective goal offinishing the routing with minimum overall wire length, minimum DRCs,etc. In other embodiments, the agents are programmed to act in a morecompetitive manner, but still seeking to complete the same overall goal.In some embodiments, a hybrid scheme is used, for example, agentsworking in teams, where the agents in a team seek to collaborate, andmultiple teams act in a competitive manner against other teams.

In some embodiments taking the MARL approach, multiple DQN’s are used(for example, one for each agent). In other embodiments, each agent isusing the same policy, so a single DQN is shared across the variousagents. Each agent however makes its own decisions, independent of theothers. This approach is known as independent Q-learning (IL-Q), andworks reasonably well in some scenarios. However, this IL-Q approachmisses the fact that interactions between agents affect the decisionmaking of each agent. For example, two agents in some embodiments makeindependent decisions that result in the routing of two nets too closeto each other, increasing the capacitance between the nets, or thelikelihood of a bridging fault, for example, depending to a degree onthe surrounding context.

In a single-agent setting, the environment is stationary, meaning thatthe distribution of the rewards in a given state is always essentiallythe same. This stationarity is violated in the multi-agent settinghowever, since the rewards received by an individual agent will vary notonly based on its own actions, but also on those of the other agents.The use of IL-Q in such nonstationary environments will significantlyimpair convergence. This could be improved upon by encoding ajoint-action space across multiple agents. In other words, instead ofreturning a one-hot action vector of size 6 (N,W,E,W,U,D) for eachagent, a 6^N (6 to the power of N) length vector is constructed, where Nis the number of agents participating in the MARL scheme. Unfortunately,this vector grows exponentially in the number of agents, i.e., thenumber of nets being concurrently routed. For example, if there are 100nets being routed, the vector would be of length 6^20, which is a largenumber.

In some embodiments therefore, the full j oint-action space isapproximated, by recognizing that only agents in close proximity to eachother will affect each other. (Nets routed close together affectcapacitance far more than nets routed far from each other. Likewise,nets routed close to each other will suffer more from pinching orbridging effects than nets routed far from each other). Hence, in someembodiments, neighborhood effects is approximated by only modeling thejoining actions of agents (nets) that are within the same opticalneighborhood. The full joint-action space is divided into a set ofoverlapping sub-spaces, and only the Q-values are computed for thesemuch smaller subspaces. For example, in some embodiments, if only theimmediate left and right lateral neighbors for a net being routed in thevertical preferred direction is considered, the approximated jointaction space is of length 6^3=216, which is tractable, rather than oflength 6^100 (intractable).

For capacitance calculations in particular, it is known in someembodiments that nets beyond the immediate east and west neighbors (forvertically routed layers) are essentially ignored. Likewise, nets whoserouting heads are beyond the immediate north and south neighbors forhorizontally routed layers are ignored in some embodiments. Hence, whencomputing the joint-action space for agent 1 (i.e., the agent routingnet 1), the 2 same-layer agents (nets) whose routing heads are currentlyclosest to those of agent 1 are found and build a j oint-action one-hotvector for these three agents in total. For each of the 100 agents (oneper net being concurrently routed), the subspace for these joint-actionvectors is built and use them to compute the Q-values for each agent.Since coupling capacitances are far more dominant thancrossover/crossunder capacitances in nanometer-geometry processes,agents whose routing heads are currently on metal layers different fromthe head of the net under consideration are also ignored in someembodiments. Further, routes on metal layers higher or lower than thelayer being manufactured have no lithographic impact, due to beingmanufactured during different process steps. Finally, the agents usethose Q-values computed from the reduced-space joint-action vectors asfor those Q-values computed in the single-agent case.

FIG. 40 conceptually illustrates an electronic system 4000 with whichsome embodiments of the invention are implemented. The electronic system4000 may be a computer (e.g., a desktop computer, personal computer,tablet computer, server computer, mainframe, a blade computer etc.),phone, PDA, or any other sort of electronic device. As shown, theelectronic system includes various types of computer readable media andinterfaces for various other types of computer readable media.Specifically, the electronic system 4000 includes a bus 4005, processingunit(s) 4010, a system memory 4025, a read-only memory 4030, a permanentstorage device 4035, input devices 4040, and output devices 4045.

The bus 4005 collectively represents all system, peripheral, and chipsetbuses that communicatively connect the numerous internal devices of theelectronic system 4000. For instance, the bus 4005 communicativelyconnects the processing unit(s) 4010 with the read-only memory (ROM)4030, the system memory 4025, and the permanent storage device 4035.From these various memory units, the processing unit(s) 4010 retrieveinstructions to execute and data to process in order to execute theprocesses of the invention. The processing unit(s) may be a singleprocessor or a multi-core processor in different embodiments.

The ROM 4030 stores static data and instructions that are needed by theprocessing unit(s) 4010 and other modules of the electronic system. Thepermanent storage device 4035, on the other hand, is a read-and-writememory device. This device is a non-volatile memory unit that storesinstructions and data even when the electronic system 4000 is off. Someembodiments of the invention use a mass-storage device (such as amagnetic or optical disk and its corresponding disk drive) as thepermanent storage device 4035.

Other embodiments use a removable storage device (such as a floppy disk,flash drive, etc.) as the permanent storage device. Like the permanentstorage device 4035, the system memory 4025 is a read-and-write memorydevice. However, unlike storage device 4035, the system memory is avolatile read-and-write memory, such a random access memory. The systemmemory stores some of the instructions and data that the processor needsat runtime. In some embodiments, the invention’s processes are stored inthe system memory 4025, the permanent storage device 4035, and/or theread-only memory 4030. From these various memory units, the processingunit(s) 4010 retrieve instructions to execute and data to process inorder to execute the processes of some embodiments.

The bus 4005 also connects to the input and output devices 4040 and4045. The input devices enable the user to communicate information andselect commands to the electronic system. The input devices 4040 includealphanumeric keyboards and pointing devices (also called “cursor controldevices”). The output devices 4045 display images generated by theelectronic system. The output devices include printers and displaydevices, such as cathode ray tubes (CRT) or liquid crystal displays(LCD). Some embodiments include devices such as a touchscreen thatfunction as both input and output devices.

Finally, as shown in FIG. 40 , bus 4005 also couples electronic system4000 to a network 4065 through a network adapter (not shown). In thismanner, the computer can be a part of a network of computers (such as alocal area network (“LAN”), a wide area network (“WAN”), or an Intranet,or a network of networks, such as the Internet. Any or all components ofelectronic system 4000 may be used in conjunction with the invention.

Some embodiments include electronic components, such as microprocessors,storage and memory that store computer program instructions in amachine-readable or computer-readable medium (alternatively referred toas computer-readable storage media, machine-readable media, ormachine-readable storage media). Some examples of such computer-readablemedia include RAM, ROM, read-only compact discs (CD-ROM), recordablecompact discs (CD-R), rewritable compact discs (CD-RW), read-onlydigital versatile discs (e.g., DVD-ROM, dual-layer DVD-ROM), a varietyof recordable/rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.),flash memory (e.g., SD cards, mini-SD cards, micro-SD cards, etc.),magnetic and/or solid state hard drives, read-only and recordableBlu-Ray® discs, ultra density optical discs, any other optical ormagnetic media, and floppy disks. The computer-readable media may storea computer program that is executable by at least one processing unitand includes sets of instructions for performing various operations.Examples of computer programs or computer code include machine code,such as is produced by a compiler, and files including higher-level codethat are executed by a computer, an electronic component, or amicroprocessor using an interpreter.

While the above discussion primarily refers to microprocessor ormulti-core processors that execute software, some embodiments areperformed by one or more integrated circuits, such as applicationspecific integrated circuits (ASICs) or field programmable gate arrays(FPGAs). In some embodiments, such integrated circuits executeinstructions that are stored on the circuit itself.

As used in this specification, the terms “computer”, “server”,“processor”, and “memory” all refer to electronic or other technologicaldevices. These terms exclude people or groups of people. For thepurposes of the specification, the terms display or displaying meansdisplaying on an electronic device. As used in this specification, theterms “computer readable medium,” “computer readable media,” and“machine readable medium” are entirely restricted to tangible, physicalobjects that store information in a form that is readable by a computer.These terms exclude any wireless signals, wired download signals, andany other ephemeral or transitory signals.

While the invention has been described with reference to numerousspecific details, one of ordinary skill in the art will recognize thatthe invention can be embodied in other specific forms without departingfrom the spirit of the invention. For instance, a number of the figuresconceptually illustrate processes. The specific operations of theseprocesses may not be performed in the exact order shown and described.The specific operations may not be performed in one continuous series ofoperations, and different specific operations may be performed indifferent embodiments. Furthermore, the process could be implementedusing several sub-processes, or as part of a larger macro process.Therefore, one of ordinary skill in the art would understand that theinvention is not to be limited by the foregoing illustrative details,but rather is to be defined by the appended claims.

1. A method of performing routing to define a plurality of routes for aplurality of nets in an integrated circuit (IC) design layout, themethod comprising: performing a first routing operation to define afirst set of one or more routes for a first set of one or more nets inthe design layout; and supplying the first set of routes to amachine-trained network (MTN) to add, in the design layout, a set of oneor more redundant via locations for a group of one or more routes in theset of routes to modify.
 2. The method of claim 1 further comprisingreceiving from the MTN a modified first set of routes that includes theadded set of redundant via locations and includes at least a first routethat the MTN modified to use a particular redundant via location thatthe MTN added.
 3. The method of claim 2, wherein the MTN is trained in atraining process that uses a first plurality of known input designlayouts with a first plurality of corresponding known output designlayouts that have one or more redundant vias added to theircorresponding input design layouts, said known input design layouts fedthrough the MTN during training to produce a second plurality ofcorresponding output design layouts that identify one or more redundantvias in their corresponding input design layouts, the second pluralityof output design layouts used in conjunction with the first plurality ofknown output design layouts to generate a loss function value, which isused to adjust a set of trainable parameters of the MTN.
 4. The methodof claim 2, wherein after the first routing operation and before thefirst set of routes are supplied to the MTN, the first route did nottraverse to a location of the particular redundant via, and after theMTN modifies the first route, the modified first route traverses to thelocation of the particular redundant via.
 5. The method of claim 4,wherein the IC design layout comprises a plurality of layers, and thefirst route traverses two layers connected by the particular redundantvia location, and the location of the particular redundant via comprisesx- and y-axis planar coordinates that specify the location of theparticular redundant via on each of the connected two layers.
 6. Themethod of claim 4, wherein the MTN is trained in a training process thatuses a first plurality of known input design layouts with a firstplurality of corresponding known output design layouts that have one ormore redundant vias added to their corresponding input design layoutsand one or more routes modified to traverse to a redundant via location,said known input design layouts fed through the MTN during training toproduce a second plurality of corresponding output design layouts thatidentify one or more redundant vias in their corresponding input designlayouts and one or more modified routes that traverse to a redundant vialocation, the second plurality of output design layouts used inconjunction with the first plurality of known output design layouts togenerate a loss function value, which is used to adjust a set oftrainable parameters of the MTN.
 7. The method of claim 2, wherein themodified design layout further specifies a different location for afirst via used by a second route, before the MTN modifies the first setof routes, the first via is at a first location in the design layout,and after the MTN modifies the first set of routes, the first via is ata second location in the design layout.
 8. The method of claim 7,wherein after the first routing operation and before the first set ofroutes are supplied to the MTN, the second route does not traverse tothe second location of the first via, and after the MTN moves the firstvia, the MTN modifies the second route to traverse to the secondlocation.
 9. The method of claim 7, wherein the MTN is trained in atraining process that uses a first plurality of known input designlayouts with a first plurality of corresponding known output designlayouts that have (i) a new location for each of one or more vias intheir corresponding input design layouts and (ii) one or more routesmodified to traverse to a new via location, said known input designlayouts fed through the MTN during training to produce a secondplurality of corresponding output design layouts that comprise (i) a newlocation for each of one or more vias in their corresponding inputdesign layouts and (ii) one or more modified routes modified to traverseto a new via location, the second plurality of output design layoutsused in conjunction with the first plurality of known output designlayouts to generate a loss function value, which is used to adjust a setof trainable parameters of the MTN.
 10. The method of claim 1, whereinsupplying the first set of routes comprises supplying a portion of theIC design layout that contains the first set of routes to the MTN.
 11. Anon-transitory machine readable medium storing a program which whenexecuted by at least one processing unit performs routing to define aplurality of routes for a plurality of nets in an integrated circuit(IC) design layout, the program comprising sets of instructions for:performing a first routing operation to define a first set of one ormore routes for a first set of one or more nets in the design layout;and supplying the first set of routes to a machine-trained network (MTN)to add, in the design layout, a set of one or more redundant vialocations for a group of one or more routes in the set of routes tomodify.
 12. The non-transitory machine readable medium of claim 11,wherein the program further comprises a set of instructions forreceiving from the MTN a modified first set of routes that includes theadded set of redundant via locations and includes at least a first routethat the MTN modified to use a particular redundant via location thatthe MTN added.
 13. The non-transitory machine readable medium of claim12, wherein the MTN is trained in a training process that uses a firstplurality of known input design layouts with a first plurality ofcorresponding known output design layouts that have one or moreredundant vias added to their corresponding input design layouts, saidknown input design layouts fed through the MTN during training toproduce a second plurality of corresponding output design layouts thatidentify one or more redundant vias in their corresponding input designlayouts, the second plurality of output design layouts used inconjunction with the first plurality of known output design layouts togenerate a loss function value, which is used to adjust a set oftrainable parameters of the MTN.
 14. The non-transitory machine readablemedium of claim 12, wherein after the first routing operation and beforethe first set of routes are supplied to the MTN, the first route did nottraverse to a location of the particular redundant via, and after theMTN modifies the first route, the modified first route traverses to thelocation of the particular redundant via.
 15. The non-transitory machinereadable medium of claim 14, wherein the IC design layout comprises aplurality of layers, and the first route traverses two layers connectedby the particular redundant via location, and the location of theparticular redundant via comprises x- and y-axis planar coordinates thatspecify the location of the particular redundant via on each of theconnected two layers.
 16. The non-transitory machine readable medium ofclaim 14, wherein the MTN is trained in a training process that uses afirst plurality of known input design layouts with a first plurality ofcorresponding known output design layouts that have one or moreredundant vias added to their corresponding input design layouts and oneor more routes modified to traverse to a redundant via location, saidknown input design layouts fed through the MTN during training toproduce a second plurality of corresponding output design layouts thatidentify one or more redundant vias in their corresponding input designlayouts and one or more modified routes that traverse to a redundant vialocation, the second plurality of output design layouts used inconjunction with the first plurality of known output design layouts togenerate a loss function value, which is used to adjust a set oftrainable parameters of the MTN.
 17. The non-transitory machine readablemedium of claim 12, wherein the modified design layout further specifiesa different location for a first via used by a second route, before theMTN modifies the first set of routes, the first via is at a firstlocation in the design layout, and after the MTN modifies the first setof routes, the first via is at a second location in the design layout.18. The non-transitory machine readable medium of claim 17, whereinafter the first routing operation and before the first set of routes aresupplied to the MTN, the second route does not traverse to the secondlocation of the first via, and after the MTN moves the first via, theMTN modifies the second route to traverse to the second location. 19.The non-transitory machine readable medium of claim 17, wherein the MTNis trained in a training process that uses a first plurality of knowninput design layouts with a first plurality of corresponding knownoutput design layouts that have (i) a new location for each of one ormore vias in their corresponding input design layouts and (ii) one ormore routes modified to traverse to a new via location, said known inputdesign layouts fed through the MTN during training to produce a secondplurality of corresponding output design layouts that comprise (i) a newlocation for each of one or more vias in their corresponding inputdesign layouts and (ii) one or more modified routes modified to traverseto a new via location, the second plurality of output design layoutsused in conjunction with the first plurality of known output designlayouts to generate a loss function value, which is used to adjust a setof trainable parameters of the MTN.
 20. The non-transitory machinereadable medium of claim 11, wherein the set of instructions forsupplying the first set of routes comprises a set of instructions forsupplying a portion of the IC design layout that contains the first setof routes to the MTN.